O HAI THIS BLOG PURPZIEZ 2 B UZED AZ MAH PLESIOUS MEM. :)

2007/12/14

ifdef.karma--; /* app-text/xpdf-3.02-r1 */

matsuuさんが蝶頑張って直したっぽいpTeXのテストも兼ねて,以前作った
日本語のPDFを見ようとしたら,app-text/xpdfがぶっ壊れている事に気づいた.
で,モニョモニョして直した. :)
[Matsuu fix0r pTeX. I tested it and seeing my Japanese PDF. But app-text/xpdf
was b0rk, I realized. So I fixed. PLZ FIX0R IN T3H TREE 2 ASAP KTHX. :)]

bug #200023

#ifdefを安易に使うなとあれほど言ったのに!!1 :P
[#ifdef considered harmful, we know!!1 :P]
Google "#ifdef considered harmful"

2007/12/06

return PowerBook;

PowerBookが修理から戻って来たのでムニャムニャするのを再開.
[My PowerBook return, it's time to restart do REALLYSOMETHING(tm).]

Nils本人からrelease announceによりoverlayのsys-devel/nwccを0.7.4にbumb.
実はrenameだけだがな!!1 :P
[I did *just* rename my overlay's sys-devel/nwcc to bumb 0.7.4!!1 :P]

media-libs/libcacaで遊ぶついでにapp-misc/toiletをemergeしようと思ったら,
MISSINGKEYWORD(tm)だったのでekeyword ~ppcしてoverlayに突っ込んだ.
いい感じにITJUSTWORKS(tm)なので,bugzieにレポった.
[To poke media-libs/libcaca, I've tried to emerge app-misc/toilet
but emerge vomits MISSINGKEYWORD(tm). So I did ekeyword ~ppc it
and pushed into my overlay. Sure, ITJUSTWORKS(tm). I filed keyword
request to bugzie, of course.]

bug #201363

で,なぜか#-bugsでネタにされる. :DDD
[Then, #-bugs dudes were going to go nuts. :DDD]
12/06 00:38:05 jeeves
[New Bug] https://bugs.gentoo.org/201363 enh, P2, PPC,
hiyuh.root.gmail.com->bug-wranglers.gentoo.org, NEW, pending, ~ppc
keyword request for app-misc/toilet (Reassign bug to drac.gentoo.org
?)
12/06 00:38:14 kojiro
say what?
12/06 00:38:32 kojiro
aargh, I really gotta pee but the toilet's MASKED
12/06 00:38:35 kojiro
halp!
12/06 00:39:56 welp
LOL
12/06 00:40:01 hiyuh
hehe
12/06 00:40:05 welp
ok, that toilet bug is just too cool :P
12/06 00:40:11 *
welp pets hiyuh
12/06 00:40:17 welp
who's a clever boy ;)
ふざけすぎてbugzieには一ヶ所typoがあるけど気にしない,気にしない. :p
[U CAN HAS INVIZIBLE MAI TYPO at the bug report. :p]

2007/11/22

echo "STFU, do code" > /me

B2なVHDLマクロをfsckin'だのjunkだのとぼやきながらモニョっていたら,
先日の人事考課の時に「お前,もう少し丁寧な言葉遣いしろよ」みたいな
事をボスに言われてしまったので,実験的に年が明けるまで会社では極力
喋らないでコーディングをしてみる事にした.
[I've been vomiting about B2's VHDL macros like, "U fsckin' XXX!!1",
"koo, t3h junk!!1" though, then my bossez sez to me, "why you can
not do STFU?". So, I'm doing STFU now in office, yup only do codin' ATM.]

で,黙る前より何かイイ感じにガリガリやれる事に気付く.
「黙ってコードを書けよ,ハゲ」ってのは多分実績に裏打ちされている. :P
[Well, I'd have to say "STFU, do code" goes a long way to increase commits,
I realized. It's now proven, "STFU, do code" is FTW. :P]

全然関係無いが,昼飯時に定食屋で見たTVでこんな事も有ったみたいで
何気に"たいむりー". :DDD
[Hmm, that' sounds like good OT news to me. :DDD]
2007 Ibero-American Summit controversy
- Juan Carlos I of Spain, Wikipedia

2007/11/05

push(&overlay, &webkit); push(&overlay, &midori);

net-libs/webkitとwww-client/midoriをoverlayに突っ込んだ.
マルチバイト文字は豆腐になるみたいなのであまり期待しないように.
とりあえず,webkitはsafari powered by appleなブツなので
気長に待つつもりならすこし期待してもいいかもね. :p
[Pushed net-libs/webkit and www-client/midori into my overlay.
But it has no multibyte capabilities ATM, I guess. B/c it won't
display multibyte character correctly. webkit is known as a part
of safari by apple. So we will see... :p]

2007/11/04

IS_BC_BUMB(bug) || IS_BC_DRUMB(bug)

bumbとdrumbは違うらしい. :DDD
[bumb is not drumb, heh. :DDD]
11/04 01:10:55 jeeves
[New Bug] https://bugs.gentoo.org/197968 min, P2, All,
felix@h.d-bug-wranglers@g.o, NEW, pending, vym installs into wrong
prefix
11/04 01:11:17 drac
bad
11/04 01:12:00 jakub
failees again :)
11/04 01:12:14 jakub
ColdWind: ^^^ :)
11/04 01:13:26 hiyuh_jabberwoch
lolz
11/04 01:14:32 ColdWind
daaamn
11/04 01:14:45 ColdWind
that's what happens when you do drunk bumps
11/04 01:16:13 eroyf
that was one of my few rules when i was a dev
11/04 01:16:24 eroyf
never enter my cvs checkout while i was drunk
11/04 01:17:40 ColdWind
I'll do some pam rules for it ;)
11/04 01:18:02 jakub
ColdWind: lol :D
11/04 01:18:07 jokey_mobile
indeed, pam rulz ;)
11/04 01:18:08 jakub
drunk bump :D
11/04 01:19:43 armin76
bumb?
11/04 01:19:49 drac
bumb.
11/04 01:19:58 hiyuh_jabberwoch
*bumb*
11/04 01:20:59 kojiro
drumb
11/04 01:22:33 bonsaikitten
Gump!
11/04 01:22:56 drac
+1 for drumb
11/04 01:23:04 drac
don't spoil our bumbs with booze.
11/04 01:23:44 kojiro
how d'you pronounce 'bumb'? Is it like "bum", or like "bumbee"?
11/04 01:24:21 ColdWind
kojiro: just bumb, can't you pronounce that? :p
11/04 01:24:34 kojiro
heh

2007/11/03

ricecmp(&me, &others) ? me.rice.karma++ : others.rice.karma++;

#-bugsにて,変な流れでrice比べに. :p
[At #-bugs, there is many fsckin' ricers who would show his uname -a to each others. :)]
11/03 22:52:50 loki_val
please do my homework for me.
11/03 22:53:35 loki_val
get_libdir; does it supply lib{,32,64} with or without finishing slash
11/03 22:53:50 jakub
see multilib.eclass :)
11/03 22:54:44 loki_val
jakub: I adore you. You're so cute when you're right.
11/03 22:55:05 pchrist
everyone adores jacub
11/03 22:56:36 *
hiyuh_jabberwoch adorez.
11/03 22:57:40 pchrist
hiyuh_jabberwoch: I liked that poem
11/03 22:58:34 Lap_64
peoms everyone we write about how to get wild on bed
11/03 22:59:29 hiyuh_jabberwoch
lolz
11/03 23:00:59 hiyuh_jabberwoch
Linux jabberwocky 2.6.21-gentoo-r3-mactel #1 SMP PREEMPT Sat Jun
30 22:36:16 JST 2007 x86_64 Intel(R) Core(TM)2 CPU T7400 @ 2.16GHz
GenuineIntel GNU/Linux
11/03 23:01:36 Lap_64
Linux localhost 2.6.20.3 #1 SMP Fri Mar 16 12:34:47 IST 2007 x86_64
AMD Turion(tm) 64 Mobile Technology MT-28 AuthenticAMD GNU/Linux
11/03 23:01:59 hiyuh_jabberwoch
heh
11/03 23:02:52 Lap_64
oink oink
11/03 23:02:55 ColdWind
loosers...
11/03 23:02:57 ColdWind
Linux localhost 2.6.23-gentoo #2 SMP PREEMPT Tue Oct 23 23:01:41 CEST
2007 i686 Intel(R) Pentium(R) 4 CPU 3.00GHz GenuineIntel GNU/Linux
11/03 23:03:23 hiyuh_jabberwoch
zomg
11/03 23:03:25 pchrist
Linux Erato 2.6.20.4 #1 SMP Sun Apr 1 18:47:23 EEST 2007 x86_64
Intel(R) Xeon(TM) CPU 3.00GHz GenuineIntel GNU/Linux
11/03 23:03:28 pchrist
what about that?
11/03 23:03:41 Lap_64
ColdWind, that doesnt make you a winner
11/03 23:03:49 jakub
pchrist: faileees as kernel ricer :P
11/03 23:03:54 ColdWind
Lap_64: no? err! faiiil
11/03 23:03:54 Lap_64
pchrist, you are next to jesus christ
11/03 23:05:05 pchrist
this is the nice part of working in a university
11/03 23:05:26 Lap_64
hehe
11/03 23:07:37 jakub
lol
11/03 23:07:56 loki_val
Linux loki 2.6.22-gentoo-r8 #1 Thu Sep 27 00:35:17 CEST 2007 i686
AMD Sempron(tm) AuthenticAMD GNU/Linux
11/03 23:08:11 loki_val
Beat that for sheer vintage glory.
11/03 23:08:18 welp
Linux dev 2.6.16.16 #2 SMP Fri Jun 30 13:52:41 CEST 2006 x86_64 AMD
Athlon(tm) 64 Processor 3200+ AuthenticAMD GNU/Linux
11/03 23:08:21 *
Lap_64 beats
11/03 23:08:22 welp
*wins*
11/03 23:08:29 pchrist
Lap_64: What I really want, is if I could be next to a new SGI
itanium machine
11/03 23:08:38 hiyuh_jabberwoch
wtf
11/03 23:08:45 *
Lap_64 claps for welp
11/03 23:08:47 jakub
armin76: where are you with your git sources? :P
11/03 23:09:45 *
loki_val twocks welp.
11/03 23:09:57 welp
twocks?! you mean thwocks, right? :P
11/03 23:10:03 Lap_64
hehe
11/03 23:10:15 pchrist
I just realized that my machine has wrong date
11/03 23:10:16 loki_val
omsgz. grammar nazi.
11/03 23:10:22 Lap_64
welp, i am afrid if he ment ahem two cocks :P
11/03 23:11:15 *
loki_val meant "cleans welps pipe".
11/03 23:11:26 loki_val
with an iron brush.
11/03 23:13:14 Lap_64
rofl

2007/11/02

ReMeasureSLOC(&ADJJV);

ADJJVのSLOCなグラフ,再び.無駄に最小自乗法を適用.
[Here is SLOC trend of ADJJV, again. w/ LSM fitting.]

仮説:
VHDLマクロのSLOCはcommit revisionに対して,
SLOC = L(1 - exp(-sqrt(revision/R)))
の様相を呈す.ここにLは(論理的な)最終release時のSLOC,Rは前の(論理的な)release時の
revisionから数えて次の(論理的な)release時の第一candidateまでの平均commit数.
[Hypothesis:
VHDL macro's SLOC trend per commit revision would be expected like,
SLOC = L(1 - exp(-sqrt(revision/R)))
where L is (logical) last release SLOC, R is average number of commit
between (logical) previous release and (logical) next release candidate
of first.]

2007/11/01

PowerBook.Keyboard.Key[eENTER] = FSCKed;

PowerBookのENTERキーがぶっ壊れた.
ターミナルでコマンドを実行する時にバチバチ無駄に気合を入れて押しているのが原因です.
ほんとうににありがとうございました(ぼーよみ). :P
[My PB's enter key is now fscked.
Guess, b/c everytime executing command in terminal, I kinda smack t3h ENTER.
Yeah, it has no effect to execute it, I know. :P ]

週末にでも修理に出すかな.
[I'd have to fix0rz it ASAP.]

2007/10/26

JunkCode.karma++; /* br10_stim.c */

問題: このコードは何でしょう? :9
[Q. This code for what? :9]
#include <stdio.h>
#include <stdint.h>

#define MSK16(i, b) ((i) & ((uint16_t)0x0001 << (b)))
#define SLL16(i, b) ((uint16_t)(i) << (b))
#define SLR16(i, b) ((uint16_t)(i) >> (b))
#define ORG16(i, b) (SLR16(MSK16((i), (b)), (b)))
#define MOV16(i, b1, b2) (SLL16(ORG16((i), (b1)), (b2)))

uint16_t br10(uint16_t i) {
uint8_t b;
uint16_t bri;

for (bri = 0x0000, b = 0; b < 10; b++) {
bri |= MOV16(i, b, (10 - 1) - b);
}

return bri;
}

int main(int argc, char *argv[]) {
uint16_t i, bri, brbri;

for (i = 0x0000; i < SLL16(0x0001, 10); i++) {
bri = br10(i);
brbri = br10(bri);
printf("%4d <-BR10-> %4d <-BR10-> %4d ... %s\n",
i, bri, brbri, (i == brbri) ? "OK" : "NG");
}

return 0;
}

2007/10/23

while(1) Xilinx.ISE->EatMEM(malloc(sizeof(void)));

会社の自分のPCのISEを8.2iか9.2iにversion bumb.bumpではありません.
最近,#-bugsではversion bum*b*が流行りです. :DDD
[Version bumb 8.2i to 9.2i of fsckin' ISE at my local work PC. It's not
typo. You can see t3h rox0rz phrase, version bum*b* at #-bugs
sometimes. :DDD]

メジャーヴァージョンが上がってメモリ効率が良くなったとか,fmax云々だの
騒いでいるけれど,決め手は8.2iのままだと例のFFT IPが今回の用途で
びみょーにbugりそうだから. :p
[T3h 9.2i sez "KK, I WONT EAT UR MEM ANYMORE", "I CAN HAS FMAX
POWERZ". But all reason of what I've bumbed to 9.2i is t3h crappy FFT
IP w/ 8.2i will have a stupid bug for this project use. *STAB* :p]

Answer Record #29427
LogiCORE Fast Fourier Transform (FFT) v4.0
Why do I see incorrect outputs when I simulate an unscaled FFT with
a point size larger than 1024, and the Complex Multiplier Optimize for
Speed option is selected?

昨日のOUTPUTIFの問題は既にモニョモニョして解決した.
現在,awk(1p)な俺様VHDLバックエンドでTSVなファイルからstimulusと
expectationの対をシコシコと生成中.
[T3h Q of OUTPUTIF is already marked as RESO FIXED in this design.
ATM, I've been codin' awk(1p) back end to generate VHDL of the
stimulus and expectation pairs from TSVs.]

週末の予定メモ.
modular texliveをモニョる.
[This weekend plan: Pokin' modular texlive.]
bug #195815

xcg.fft.spec.karma--; /* fsckin' misprints */

XilinxのFast Fourier Transform v4.0のProduct specificationが低品質過ぎる.
タイミングチャートのport名が全然違うとか何考えてんだ?まじありえねー. :P
[Xilinx's Fast Fourier Transform v4.0 Product specification really suX0rz.
*STAB*. Why on the earth did dudes misprint t3h port names on timing chart?
NFC at all, KTHXBYE. :P]

で,なんとかその辺を誤魔化して,件のFFTマクロをでっち上げて,後方互換性の為に
そのまんま入出力のIFを移植した.で,予想通り,動作予定クロックで動かないと言う罠.
以下,出力IFの簡易ヴァージョンとヤル気の無いテストベンチ,さらにその手の人しか
解けないかもしれない問題っぽいモノ.
[For fsckin' backward compat, I've ported previous I/F w/o explicit changes to
t3h FFT macro by using that crap. Yup, ITDOESNTWORK(tm) w/ planning clock
ATM. These are stripped version output IF, dumb test bench, and a practical
VHDL Q.]

問題:どこがクロック高速化のボトルネックか?出来れば修正を施して示せ.
なお,OUTPUTIF.vhdlへの修正はoDATA,oOVRそれぞれのレイテンシー
は適当に増やして構わないが,修正以前と同様にアラインメントが揃っている
と好ましい.
[Q: Whre is fsckin' bottleneck to increase clock speed? Fix0rz it. You can
increase latencies of oDATA and oOVR as you like, and to sort their
alignment would be good for following ones.]

修正:typoとか.
[FIX: for typos.]
--
-- OUTPUTIF.vhdl
--
library ieee;
use ieee.std_logic_1164.all;

entity OUTPUTIF is
port (
iCLK : in std_logic;
iCLR : in std_logic;
iDATA : in std_logic_vector(22 downto 0);
iGAIN : in std_logic_vector( 3 downto 0);
oDATA : out std_logic_vector(11 downto 0);
oOVR : out std_logic
);
begin
end entity OUTPUTIF;

architecture RTL of OUTPUTIF is

begin

-- Tune Gain and OVeRflow detection
P_TG_OVR : process (iCLK)
begin
if (iCLK'event and iCLK = '1') then
if (iCLR = '1') then
oDATA <= (others => '0');
oOVR <= '0';
else
case iGAIN is
when "0000" => -- 2^0
oDATA <= iDATA(22 downto 11);
oOVR <= '0';
when "0001" => -- 2^1
if (iDATA(22 downto 21) = "00" or
iDATA(22 downto 21) = "11") then
oDATA <= iDATA(21 downto 10);
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "0010" => -- 2^2
if (iDATA(22 downto 20) = "000" or
iDATA(22 downto 20) = "111") then
oDATA <= iDATA(20 downto 9);
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "0011" => -- 2^3
if (iDATA(22 downto 19) = "0000" or
iDATA(22 downto 19) = "1111") then
oDATA <= iDATA(19 downto 8);
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "0100" => -- 2^4
if (iDATA(22 downto 18) = "00000" or
iDATA(22 downto 18) = "11111") then
oDATA <= iDATA(18 downto 7);
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "0101" => -- 2^5
if (iDATA(22 downto 17) = "000000" or
iDATA(22 downto 17) = "111111") then
oDATA <= iDATA(17 downto 6);
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "0110" => -- 2^6
if (iDATA(22 downto 16) = "0000000" or
iDATA(22 downto 16) = "1111111") then
oDATA <= iDATA(16 downto 5);
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "0111" => -- 2^7
if (iDATA(22 downto 15) = "00000000" or
iDATA(22 downto 15) = "11111111") then
oDATA <= iDATA(15 downto 4);
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "1000" => -- 2^8
if (iDATA(22 downto 14) = "000000000" or
iDATA(22 downto 14) = "111111111") then
oDATA <= iDATA(14 downto 3);
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "1001" => -- 2^9
if (iDATA(22 downto 13) = "0000000000" or
iDATA(22 downto 13) = "1111111111") then
oDATA <= iDATA(13 downto 2);
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "1010" => -- 2^10
if (iDATA(22 downto 12) = "00000000000" or
iDATA(22 downto 12) = "11111111111") then
oDATA <= iDATA(12 downto 1);
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "1011" => -- 2^11
if (iDATA(22 downto 11) = "000000000000" or
iDATA(22 downto 11) = "111111111111") then
oDATA <= iDATA(11 downto 0);
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "1100" => -- 2^12
if (iDATA(22 downto 10) = "0000000000000" or
iDATA(22 downto 10) = "1111111111111") then
oDATA <= iDATA(10 downto 0) & '0';
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "1101" => -- 2^13
if (iDATA(22 downto 9) = "00000000000000" or
iDATA(22 downto 9) = "11111111111111") then
oDATA <= iDATA(9 downto 0) & "00";
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "1110" => -- 2^14
if (iDATA(22 downto 8) = "000000000000000" or
iDATA(22 downto 8) = "111111111111111") then
oDATA <= iDATA(8 downto 0) & "000";
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when "1111" => -- 2^15
if (iDATA(22 downto 7) = "0000000000000000" or
iDATA(22 downto 7) = "1111111111111111") then
oDATA <= iDATA(7 downto 0) & "0000";
oOVR <= '0';
else
oDATA(11) <= iDATA(22);
oDATA(10 downto 0) <= (others => not iDATA(22));
oOVR <= '1';
end if;
when others => -- 2^0
oDATA <= iDATA(22 downto 11);
oOVR <= '0';
end case;
end if;
end if;
end process P_TG_OVR;

end architecture RTL;

--
-- BENCH_OUTPUTIF.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity BENCH_OUTPUTIF is
begin
end entity BENCH_OUTPUTIF;

architecture BENCH of BENCH_OUTPUTIF is

component OUTPUTIF is
port (
iCLK : in std_logic;
iCLR : in std_logic;
iDATA : in std_logic_vector(22 downto 0);
iGAIN : in std_logic_vector( 3 downto 0);
oDATA : out std_logic_vector(11 downto 0);
oOVR : out std_logic
);
end component OUTPUTIF;

signal sCLK : std_logic;
signal sCLR : std_logic;
signal sDATA : std_logic_vector(22 downto 0);
signal sGAIN : std_logic_vector( 3 downto 0);

signal sOUTPUTIF_oDATA : std_logic_vector(11 downto 0);
signal sOUTPUTIF_oOVR : std_logic;

begin

P_CLK : process
begin
sCLK <= '1'; wait for 0.5 us;
sCLK <= '0'; wait for 0.5 us;
end process P_CLK;

P_CLR : process
begin
sCLR <= '1'; wait for 10.0 us;
sCLR <= '0'; wait;
end process P_CLR;

P_DATA : process (sCLK)
begin
if (sCLK'event and sCLK = '1') then
if (sCLR = '1') then
sDATA <= (others => '0'); -- signed zero
else
sDATA <= signed(sDATA) + 1;
end if;
end if;
end process P_DATA;

P_GAIN : process (sCLK)
begin
if (sCLK'event and sCLK = '1') then
if (sCLR = '1') then
sGAIN <= (others => '0'); -- unsigned zero
else
if (signed(sDATA) = 0) then
sGAIN <= unsigned(sGAIN) + 1;
else
sGAIN <= sGAIN;
end if;
end if;
end if;
end process P_GAIN;

U_OUTPUTIF : OUTPUTIF
port map (
iCLK => sCLK,
iCLR => sCLR,
iDATA => sDATA,
iGAIN => sGAIN,
oDATA => sOUTPUTIF_oDATA,
oOVR => sOUTPUTIF_oOVR
);

end architecture BENCH;

2007/10/18

Suspend(&ADJJV); read(xcg.fft.spec, &me, ALL);

ADJJVが一段落,まだおわってないけど.記念にあとでSLOCのグラフも作っとくかな.
[I'd suspend to be codin' ADJJV, (is not completed yet). I'll make its
SLOC trend graph as a ceremonial crap soonish.]

続いて,XilinxのCoreGenのFFTの英語な仕様書を読む予定.
なんでも,あるブツがLX200なボードに入りきらんので,FFTの部分をソイツに取り替えた上で,
動作速度を上げる事で回路容量を減らすんだとか.
ボス曰く,ストリーム処理の回路容量を減らす為に,多入力多出力同一回路を単一回路にして,
動作速度をその分上げて,入力後段MUX+FIFOと出力前段にDEMUX+FIFOな感じすればいい,と.
今でも128MHzで動いてるのにホントに大丈夫なんかな? :9
[Then, I'd have to read fsckin' Xilinx CoreGen's FFT spec written in English.
To diet bloated t3h macro, my bosses sez "multiple input/output macro
has some identical inside sub-macro, FFT that is. The plain is to rip it
for making it be unified. Plus, input MUX+FIFO and output DEMUX+FIFO,
then input faster clock, period."
...Oh dear, I'd have to say "yes sir", but WTF? :)]

2007/10/14

bus(eBIDIRECT).collison.karma--;

#vhdl@irc.freenode.netで双方向バスの話.
[Here is snippet log of #vhdl@irc.freenode.net.
The subject is bidirectional bus.]
10/13 23:48:13 joe2371
I do not understand iobuf. What happens if I is driven to (NOT IO)?
Which input wins?
10/13 23:50:28 joe2371
Would this condition tie Vcc to ground?
10/13 23:57:15 joe2371
Do I use T to select input vs. output mode? The table I have in my
documentation does not make this clear to me.
10/14 00:08:35 joe2371
I am going to assume that the table is simply unclear and the
schematic symbol probably represents a combination of obuft with
ibuf. That would make a lot of sense, but I am surprised that the
Xilinx documentation would describe the operation the way it does.
Unless my original interpretation of the documentation is correct and
I need to use seperate ibuf and obuft components in my design. Ugh.
10/14 00:23:54 joe2371
Please look at this and tell me if I am right or wrong. Thank
you. http://rafb.net/p/y1DT3Y68.html
10/14 00:30:40 joe2371
Hans, can you please answer my question if you have time?
http://rafb.net/p/y1DT3Y68.html
(BEGIN_SNIPPET_FROM_THE_LINK)
iobuf

T ____
|
|\|
I __| \______ IO
| / |
|/ |
/| |
O ___/ |__|
\ |
\|


Xilinx iobuf table:

T I IO O
1 X Z X
0 1 1 1
0 0 0 0

But I think I want this:

T I IO O
1 X 0 0
1 X 1 1
0 0 0 X
0 1 1 X

Is this what I get?
(END_SNIPPET_FROM_THE_LINK)
10/14 00:31:57 joe2371
I am trying to learn how to use the iobuf component and the
documentation is not clear to me.
10/14 00:33:12 joe2371
And I don't know how to test my understanding in simulation because
it is a buffer.
10/14 01:31:34 hiyuh
joe2371: did you understand...
10/14 01:31:46 hiyuh
1. "I is input from inside of FPGA, to output to IO"?
10/14 01:31:53 hiyuh
2. "O is output from outside of FPGA, to input from IO"?
10/14 01:31:55 hiyuh
3. "buffered I and unbuffered O is shared at inside of FPGA"?
10/14 01:32:33 joe2371
IO is pin side. I,O are FPGA side, right?
10/14 01:32:47 hiyuh
yup
10/14 01:33:23 joe2371
does T select input/output mode? I mean, what happens if I is 0
but IO goes to 1?
10/14 01:35:19 joe2371
I mean, if SRAM is driving IO, how do I disable I from trying to
drive it also?
10/14 01:36:08 joe2371
Do I have to output Z to the I?
10/14 01:37:07 hiyuh
nope, T selects buffered I's state (it may not be IO's state) to 'Z'
(T = 1) or unbuffered I (T = 0).
10/14 01:38:13 joe2371
So T disables the I pin of the iobuf, but does prevent IO from
changing O?
10/14 01:40:12 joe2371
I am trying to learn how to read the value of IO into the FPGA.
10/14 01:42:06 joe2371
I guess I still don't understand. And I have not been able to simulate
an iobuf to learn how it works. :-/
10/14 01:44:20 joe2371
Maybe you have answered my question already. If T=1 makes I=Z,
then hopefully O=IO.
10/14 01:45:46 joe2371
I am sorry if I do not immediately understand your explanation.
10/14 01:52:39 hiyuh
"if T <= 1, then buffered I <= 'Z' and O <= IO", "if T =
0, buffered I <= I. so O and IO <= wired(buffered I, IO comes
from as others' output)"
10/14 01:53:44 joe2371
Thank you. I think that is exactly what I want.
10/14 01:53:55 hiyuh
yw
10/14 01:57:27 hiyuh
... so bus collision make your day, I guess. :p
10/14 01:57:35 hiyuh
s/make/makes/
10/14 01:57:36 *
hiyuh runs.
10/14 01:59:37 hiyuh
FYI, to read about "I-BEFORE" and "OUT-AFTER" for ucf files' timing
constrain would be useful.
10/14 01:59:53 hiyuh
s/I-/IN-/
10/14 02:00:31 joe2371
oh, no. This means "O and IO <= wired(I, IO comes from SRAM)"
means two inputs on same bus. That is not what I want, of course.
10/14 02:01:34 hiyuh
yeah
10/14 02:02:13 joe2371
"assign IO = I and assign IO = SRAM-output" at the same time is not
what I want. Does this mean I cannot use iobuf for my design?
10/14 02:03:05 joe2371
I will look for "I-BEFORE" and "OUT-AFTER" for ucf files.
10/14 02:07:54 hiyuh
so, to keep IO <= 'Z' w/ T = '1' as neutral. when you really want
to output via IOBUF, make sure SRAM is input-state before output
via IOBUF. when others, you should think SRAM may be output-state.
10/14 02:08:53 joe2371
oh, I see.
10/14 02:08:56 hiyuh
otherwise, bus collisoin makes your day. :p

2007/10/13

snipLog("/me@#vhdl");

久しぶりにIRCのログを貼り付けてみる.
#vhdl@irc.freenode.netでMemory I/Fなお話.
[Here is a snippet log #vhdl@irc.freenode.net. The subject is a memory I/F.]
10/13 04:14:34 joe2371
Are questions about schematics portable between languages and
software? I'm trying to find out the correct way to connect one
signal to two FPGA pins. Do I want to treat my signal as a 1-bit bus
and put two taps on it? I thought that bus taps required the nets
on both sides to have compatible names (eg: Addr(19:0) -> Addr(15)
and not Addr(19:0) -> Foo). Is this splitting best done in the pin
assignment file (.ucf) ?
10/13 04:28:44 hiyuh
depends on transfer speed, imho.
10/13 04:32:33 hiyuh
e.g. I'm now working 8 boards (each one has 4 virtex4).
10/13 04:33:21 hiyuh
each virtex4 will input/output from/to others, the data syncs 128MHz
via simple parallel bus.
10/13 04:33:26 hiyuh
the output to outside of the board will be syncs 256MHz as LVDS.
10/13 04:33:38 hiyuh
sample pic is http://dev.gentoo.gr.jp/~hiyuh/misc/V4LXB.jpg
10/13 04:35:12 hiyuh
reference clock's accuracy and deskewing of sync clock is also PITA.
10/13 04:35:32 hiyuh
s/is/are/
10/13 04:38:47 joe2371
That's a nice looking board. The Virtices have fans on them?
10/13 04:39:58 hiyuh
yup
10/13 04:41:38 hiyuh
the left side one is japanese tobacco box, btw.
10/13 04:41:59 joe2371
With the letter C ?
10/13 04:42:10 hiyuh
yeah
10/13 04:43:12 joe2371
pretty neat. I'd hate to think what it costs.
10/13 04:44:27 joe2371
Do tools exists that can map a design across multiple chips
automatically?
10/13 04:45:51 joe2371
...basically treating four FPGAs like one larger one, I mean.
The more I think about it, the less likely I imagine that is.
10/13 04:46:02 hiyuh
my bosses said, one Virtex4 LX200 (the best one of Virtex4 LX series)
will costs about 1000000 yen. but it should depends on quantities
of order, I guess. :p
10/13 04:47:05 joe2371
It's something like 1000 yen to the dollar, I think. Ouch.
10/13 04:47:43 hiyuh
I dunno that neat tool which automatically map it to them.
10/13 04:48:29 joe2371
I guess if they are Virtex chips, you are stuck with Xilinx tools.
10/13 04:49:39 hiyuh
yeah, it's kinda corporate (or project's?) policy, maybe.
10/13 04:50:48 hiyuh
so I can take a screenshot of fsckin' ISE crashing per working day. :p
10/13 04:51:15 joe2371
Only once per day? ISE crashes sometimes 3-5 times on me.
10/13 04:51:50 joe2371
At least it recovers my work OK. (so far)
10/13 04:52:49 hiyuh
I'd have to treat that crap *gently*, b/c it's my job atm. :p
10/13 04:55:31 hiyuh
well, using same name in sch and logical vhdl design is a bit of
difficult, if it's a dead-lined project.
10/13 04:57:03 hiyuh
and ucf craps are not only for constraining the pin assign.
10/13 04:57:40 hiyuh
splitting them to ucf is a good way to go, though.
10/13 04:57:44 joe2371
Ok. My lab homework assignment is to create a 1MB memory controller
with only 14 address pins. I am trying to connect one signal to
two memory chips (same signal, different pins).
10/13 04:58:04 hiyuh
heh
10/13 04:58:09 joe2371
I created that 1-bit bus with two taps.
10/13 04:58:16 joe2371
I don't know if it works, though.
10/13 05:00:58 hiyuh
have you consider about the memories' I/F, driving load, or something?
10/13 05:01:19 hiyuh
s/consider/considered/
10/13 05:02:16 joe2371
oh, no. I am still experimenting with my initial concept for
the design. I don't know what difficulties to expect.
10/13 05:03:31 hiyuh
ah, ok. then first step is to gaze the memories' spec sheet, I
guess. :)
10/13 05:03:49 joe2371
The documentation for the board did not talk about driving load
that I can remember. It just says which pins of the FPGA are tied
to which pins of the SRAMs
10/13 05:04:04 joe2371
I have the specs for the SRAM here
10/13 05:05:17 hiyuh
SRAM? then it doesn't need to be refreshing, right?
10/13 05:05:25 joe2371
right
10/13 05:05:39 joe2371
yes, I am lucky it is SRAM
10/13 05:06:18 joe2371
But I am unlucky I have only 14 address bus pins connected.
10/13 05:07:50 hiyuh
SRAM's address is 14bits?
10/13 05:08:02 hiyuh
or you have only 14bits on FPGA to specify SRAM's address but SRAM's
address is not 14bits?
10/13 05:09:38 joe2371
no, 18 bits for a 16-bit memory location, plus upper byte and lower
byte pins, plus there are two chips. So SRAMs actually have 20-bit
address (of bytes). But I have a CPU which has only 14 address pins
connected to the FPGA.
10/13 05:10:12 joe2371
I want to use the LSB of the address to select upper/lower byte.
And LSB+1 to select SRAM0/SRAM1.
10/13 05:10:34 joe2371
the missing MSBits are provided from a register tied to a port.
10/13 05:11:16 joe2371
but I need to connect the LSB and LSB+1 to four pins.
10/13 05:11:28 hiyuh
oic
10/13 05:14:44 joe2371
I just thought of something. If chip enable is off, these SRAMs
go to low power mode. Maybe I should organize my pins differently
so that I will use less power when the memory is less than half
full... Hmmm... I'll think about that.
10/13 05:16:22 joe2371
I think it means changing one line of HDL. Then I can say my design
not only works, but is also efficient. :-)
10/13 05:17:43 joe2371
Nevermind. CE only goes high on reads and writes. It does not
matter if the memory contains data. (/me needs more coffee)
10/13 05:17:56 hiyuh
yeah, "separated CEs and shared others" sound good to me though.
10/13 05:18:38 joe2371
the data pins are not shared, though. Address pins are. But UB/LB/CE
are not shared either.
10/13 05:21:26 joe2371
the SRAM data sheet talks about "test load" only.
10/13 05:21:49 hiyuh
I guess "when CE is disabled, it doesn't care other signals". why
not shared address/data bus for that?
10/13 05:22:19 joe2371
They want you to be able to read 32 bits at one time, I think.
10/13 05:22:31 hiyuh
ah ok
10/13 05:23:25 joe2371
they do have shared address, though.
10/13 05:23:40 hiyuh
heh
10/13 05:25:25 joe2371
Since the connection between SRAM and FPGA cannot be changed, then I
think I can't think of anything I can do about the load from inside
the FPGA.
10/13 05:26:08 joe2371
s/I\ think\ I\ can't\ think\ of/I can't think of/
10/13 05:26:23 hiyuh
well, the spec sheet should have typ val of rw timing by pic or
table. so all what you do may be to constrain some timing of FPGA's
output.
10/13 05:27:05 joe2371
The SRAM is about 200 times faster than my CPU and is almost as fast
as the FPGA.
10/13 05:29:02 joe2371
My guess is that the SRAM will provide data long before the CPU
tries to read it. I hope I don't have too many timing problems.
10/13 05:31:57 hiyuh
deskewing for I/O like feedback path may have many timing problems,
too bad. ;p
10/13 05:33:10 hiyuh
only for output has little problem of timing (like for D/A), iirc.
10/13 05:33:40 joe2371
Do you know somewhere I can read more about this?
10/13 05:33:47 joe2371
What should I search for?
10/13 05:35:02 hiyuh
deskewing is common issue for FPGA design, see I/O and clock
management section of your device's users guide.
10/13 05:35:12 joe2371
oh, ok
10/13 05:35:20 hiyuh
good luck :)
10/13 05:35:34 joe2371
thanks. :-/
10/13 05:37:49 joe2371
"skew" was not found in the documentation. :-/
10/13 05:39:32 hiyuh
lol, what's your device?
10/13 05:40:08 joe2371
Digilent starter board with spartan3
10/13 05:42:35 joe2371
I found this in a referenced document "Digital Clock Managers also
eliminate clock skew"
10/13 05:43:19 hiyuh
yeah, DCM is a way for deskewing. :)
10/13 05:44:06 joe2371
I have 4 of them, it looks like.
10/13 05:47:19 hiyuh
well, maybe you want to use DCM_BASE or DCM_PS, I guess.
10/13 05:47:36 joe2371
I'll look them up. Thanks.
10/13 05:47:51 hiyuh
yw

Xilinx.ISE.karma--; /* MSVC++ runtime error!!1 */


今日のクラッシュ,もう何も言うまいて. :p
[Today's crash. All what I can say is only "WTF". :p]

2007/10/12

JunkCode.karma++; /* csa_stim.c */

問題: このコードは何でしょう? :9
[Q. This code for what? :9]
#include <stdio.h>
#include <stdint.h>
#include <string.h>

uint8_t do_csa(uint8_t *pa, uint8_t *pb)
{
uint8_t a_xor_b, a_and_b;

a_xor_b = *pa ^ *pb;
a_and_b = *pa & *pb;

*pa = a_xor_b;
*pb = a_and_b << 1;

return (a_and_b >> 7);
}

char *uint8_to_str(char *pstr, uint8_t q)
{
switch (q & (uint8_t)0xF0) {
case (uint8_t)0x00 : strcpy(&pstr[0], "0000"); break;
case (uint8_t)0x10 : strcpy(&pstr[0], "0001"); break;
case (uint8_t)0x20 : strcpy(&pstr[0], "0010"); break;
case (uint8_t)0x30 : strcpy(&pstr[0], "0011"); break;
case (uint8_t)0x40 : strcpy(&pstr[0], "0100"); break;
case (uint8_t)0x50 : strcpy(&pstr[0], "0101"); break;
case (uint8_t)0x60 : strcpy(&pstr[0], "0110"); break;
case (uint8_t)0x70 : strcpy(&pstr[0], "0111"); break;
case (uint8_t)0x80 : strcpy(&pstr[0], "1000"); break;
case (uint8_t)0x90 : strcpy(&pstr[0], "1001"); break;
case (uint8_t)0xA0 : strcpy(&pstr[0], "1010"); break;
case (uint8_t)0xB0 : strcpy(&pstr[0], "1011"); break;
case (uint8_t)0xC0 : strcpy(&pstr[0], "1100"); break;
case (uint8_t)0xD0 : strcpy(&pstr[0], "1101"); break;
case (uint8_t)0xE0 : strcpy(&pstr[0], "1110"); break;
case (uint8_t)0xF0 : strcpy(&pstr[0], "1111"); break;
default : strcpy(&pstr[0], "????"); break;
}

switch (q & (uint8_t)0x0F) {
case (uint8_t)0x00 : strcpy(&pstr[4], "0000"); break;
case (uint8_t)0x01 : strcpy(&pstr[4], "0001"); break;
case (uint8_t)0x02 : strcpy(&pstr[4], "0010"); break;
case (uint8_t)0x03 : strcpy(&pstr[4], "0011"); break;
case (uint8_t)0x04 : strcpy(&pstr[4], "0100"); break;
case (uint8_t)0x05 : strcpy(&pstr[4], "0101"); break;
case (uint8_t)0x06 : strcpy(&pstr[4], "0110"); break;
case (uint8_t)0x07 : strcpy(&pstr[4], "0111"); break;
case (uint8_t)0x08 : strcpy(&pstr[4], "1000"); break;
case (uint8_t)0x09 : strcpy(&pstr[4], "1001"); break;
case (uint8_t)0x0A : strcpy(&pstr[4], "1010"); break;
case (uint8_t)0x0B : strcpy(&pstr[4], "1011"); break;
case (uint8_t)0x0C : strcpy(&pstr[4], "1100"); break;
case (uint8_t)0x0D : strcpy(&pstr[4], "1101"); break;
case (uint8_t)0x0E : strcpy(&pstr[4], "1110"); break;
case (uint8_t)0x0F : strcpy(&pstr[4], "1111"); break;
default : strcpy(&pstr[4], "????"); break;
}

return pstr;
}

int main(int argc, char *arcv[])
{
uint8_t a, b;
uint8_t a_add_b;
uint8_t a_csa, b_csa;
uint8_t n_csa;
char a_str[] = "00000000";
char b_str[] = "00000000";

for (a = 0; a < (uint8_t)0x80; a++) {
for (b = 0; b < (uint8_t)0x80; b++) {
a_add_b= a + b;

a_csa = a;
b_csa = b;
n_csa = 0;
do {
printf(" CSA(%s, %s)",
uint8_to_str(a_str, a_csa),
uint8_to_str(b_str, b_csa));
do_csa(&a_csa, &b_csa);
n_csa++;
printf(" = (%s, %s) ... %d\n",
uint8_to_str(a_str, a_csa),
uint8_to_str(b_str, b_csa), n_csa);
} while (b_csa != (uint8_t)0x00);

printf("%02X | %02X || %02X | %02X || %s\n",
a, b, a_add_b,
a_csa, (a_add_b != a_csa) ? "NG" : "OK");
}
}

return 0;
}

2007/10/10

Xilinx.ISE.karma--; /* Stack corrupted!!1 */

ISEが低品質過ぎます,仕事じゃなかったらこんなブツは速攻でabandonだな. :(
[ISE really suXX0rz!!1 All why the hell I can not abandon this crap is b/c it's my job ATM.]

何してたかと言うと,200bitsのバスを隣のFPGAに突っ込むので,ボード上でのタイミング制約
を課す為に物理パッドの論理集合を作っていた.
どうみても固定長配列での集合演算ルーチンです,本当にありがとうございました. :P
[So what I did is to create logical group from physical pads to constrain
bus I/O timing between 2 FPGAs.
That *is* fsckin' set operation routines w/ fixed length array, thank god. :p]

修正:
slangだらけの英語追加.
[Add fskin' my Eng'r'ish.]

2007/10/07

GentooJP.NomiKai++; /* OSC 2007 Fall */

京急蒲田の辺りでOSC 2007 Fallでした.
[OSC 2007 Fall @ Keikyu-Kamata.]

今回は開始早々から遥々福井県からmasayukoさん達が参加してくれました.
masayukoさんはGentooJP Java leadな方です,多分. :p
[Dudes came from Fukui-pref. masayuko, AKA GentooJP Java lead... J/K. :p]

展示の方はamd64, x86, ppcのノートPC三台で,全てがタイル型ウィンドウマネージャ
(awesome x2, wmii x1)と言う基本構成で,matsuuさんはデモ用にLive CD 2007.0
も動作させていました.両隣のNetBSDの中の人達やsuseの中の人達とムニャヘニャしつつ,
「にーはお」と言う変な中華料理屋でのお昼を挟んで展示を見に来て頂いた人達にebuildの中身
を説明したり,SH*な人にアドバイスしたりとか.
[Exhibiting w/ 3 laptops. amd64, x86 and ppc, all laptop is running w/ tiling
window manager (awesome x2, wmii x1). Of course, we did w/ Live CD 2007.0
to demo. Talking w/ NetBSD and suse dudes sometimes. Lunch at "Ni-Hao".
And I've explained ebuild inside or minor arch maintenance policy for FreeBSD
and SH* guys.]

夕方からは飲み会.とりあえず,idaniさんの案内で蒲田の手羽先なお店に入った.
trombik先生のOpenBSD節を基本に,レイヤの高いお話などなどが展開されておりましたので,
レイヤの低い私には理解出来ない所が多々ありましたが,そんな事は気にしません. :D
[OSC was over, then we went to do NomiKai, first one is Tebasaki by idani.
Trombik talk passionately about OpenBSD, and something about higher layers'
that's what I can not understand a bit, but it's not problem. :D]

で,trombik先生オススメ(?)の冥土喫茶に突撃したが,満席と言う罠.
「いってらっしゃいませ,ごしゅじんさま」ってマジで言うのか. :DDD
[Then, trombik leads to his favorite Maid-Cafe.
But all the tables have been taken.
"itte rassyai mase, goshujin-sama" really rock0rz. :DDD]

更に,お好み焼き屋で二次会.
北海道vs福井県とか,日本はもうダメだとか,でも日本のお笑いには将来性があるとか,
スカパーのディスカバリーチャンネルを見ていると仕事にならねーとか.
[Second one is Okonomi-Yaki.
Hokkai-Do vs Fukui-Pref, Japan has no IAP but Japanese comedy has IAP,
Discovery channel of sky prefect TV made us sometimes "WTF".]

masayukoさんは日曜日にお子さんの運動会があるので,10時位に切り上げ.
上野まで御一緒させてもらいました.それから夜行列車で福井まで戻るそうで,大変だ!
乗り換えギリギリまでjavaの話とかをしていたので慌しくなってしまいましたが,
また話が出来ればいいですね. ;)
["Time to call it a night", at about 10:00 PM.
I came back w/ masayuko till the train arrived at Ueno.
We've been talking about java or something, so masayuko almost
missed its stop, though. Let's get together soon. :)]

2007/10/06

LX200 = pow(10, 6) * YEN; pOSC->bugz(eLIVE);


今,遊んでいるVirtex4なブツ.
[This is Virtex4 board I'm codin' for.]

Virtex4はLX, SX, FXの三種類,それぞれロジック,DSPとメモリ,I/Oに特化している(らしい).
LX200はLXシリーズの最高クラスのブツ.で,こいつLX200が四つ載っている.
LX200は百万円/個だとボスが言っていた.つまり,ボード一枚の部品代で四百万円.
そんなんが八枚もこの青い箱の中に入っている. :DDD
[Virtex4 has 3 series LX, SX and FX. They are for logic performance,
DSP and memory, I/O oriented. LX200 is highest one of LX series.
This board has 4 LX200s. LX200 costs about 1000000 yen, my bosses said.
Well, so 8 boards are in this blue box, so WTF? :DDD]

で,その蝶高級ボードに突っ込む予定のヘタレVHDLはこんな感じでSLOCが膨れ上がっています. :)
[An VHDL test sources for t3h boards are being now bloated by me. :)]


ところで明日はOSCです.bugdayな感じでテキトーにやりますのでヒマな方はお越し下さい. :)
[BTW, 10/6 is OSC, it will be bugday. Let us fix0rz bugz? :)]

2007/10/02

I HAS 1337 VHDL. LOL!!1


この野郎,思わず爆笑しそうになったじゃねーか!!1 :DDD
[WTF, I'D LOLZ!!1 :DDD]

2007/09/21

goto PinAssignHell;


イルカよ,お前が最後の頼りだ!11 :DDD
[OH MY DOLPHIN, PLZ HALP ME!11 :DDD]

buildOK(mfdlibm) ? me.karma++ : me.karma--;

やっと-std=c99 -pedantic-errorsでビルド出来る様になった. :)
なお,テストはしていないので,動作は保証出来ません. :p
[w00t, mfdlibm can be build w/ -std=c99 -pedantic-errors. :)
But IT JUST WORKS(tm), is not tested yet. :p]
mfdlibm mercurial repository

2007/09/19

Xilinx.Virtex4.UCF.karma--; fdlibm.lvalue.karma--;

ブツの製品検査の為にVirtex4が四つほど載っているボードのテスト用ファームウェアをムニャる.
[Poking Virtex4 x4 board w/ its firmware for inspection.]

ボードは全部で8枚,Virtex4が1個あたり800~900本ほど最上位層のVHDL entityから物理配線
制約を課すUCFなファイルを生成,と言うか改造.
今回使用するブツは改版後のモノで,改版前のUCFなファイルをあちこち修正する必要があった.
40ページの改版前の回路図と改版後の回路図と12時間ほど格闘.
で,やっと内部配線のチェックが出来るくらいまで修正した. :)
[Planning to use 4 boards for t3h B2. Each Virtex4's top VHDL entity has about
800 ~ 900 bits signal. So I'd have to modify the previous UCF file to constrain
physical pin assign. Gazing previous and current schematics which has A4 x40 in
about 12 hours. Finally, IT JUST WORKS(tm). :) But it's only for internal
connections inspection ATM.]

fdlibmを引き続きムニャっている.
[Poking fdlibm, as well.]
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define __HI(x) *(1 + (int*)&x)
#elif __BYTE_ORDER == __BIG_ENDIAN
#define __HI(x) *(int*)&x
#endif

...

double z;
__HI(z) ^= 0x80000000;

...

コイツぁ,ひどいlvalueですね. ;p
こんなのを見た時はコイツを引用したくなる. :DDD
[ZOMG, how nice lvalue abusing... ;p
Well, this nice pic is kinda my feeling. :DDD]
128320993454987500dudewaitw.jpg

2007/09/18

Xilinx.Virtex4.DSP48.karma--;

AGC B2 forkを予定動作クロックで動く様にグローバルクロック制約付きでISEにてモニョる.
具体的に言うと,突っ込む予定のVirtex4なFPGAの中にあるDSPになる様に結合乗加算やら
結合加乗算をFFで分離したり,運用で対処出来る範囲でコンパレータのbit幅を縮めたり.
[Poking AGC B2 fork w/ working (planning) global clock on fscking ISE.
So, isolate fused multiply-add/add-multiply, or shrinking comparator
bit length to push into Virtex4's internal DSP.]

で,結局,受信側PHY下位層で動くブツは,予定動作クロック128MHzに対して130MHz.
送信側PHY下位層で動くブツは,予定動作クロック256MHzに対して,141MHz.
やっぱ,256MHzは無理やん.中のDSPは500MHzで動くとか言っとるらしいけど,
たぶんハッタリと見た. :DDD
[Finally, I did the one which function at where lower layer than reception
PHY will function w/ 130MHz (planning clock is 128MHz), and the one at where
lower layer than transmission PHY will function w/ 141MHz (planning clock is
256MHz). Bah, it might be impossible to function w/ 256MHz to me. *stab*.
T3h fscking DSP won't function w/ 500MHz, unlike t3h spec saz.
/me failz. :DDD]

つーか,後者は配線遅延が既に六割を越えてるし,オーバーサンプリング前のクロックで
動かす方向で検討せねばならんね,コイツは. :p
[Well, the latter's route delay takes over six out of ten. There is no way to
make it capable, I guess. I should reconsider to make it function at where
pre-oversampling domain. :p]

2007/09/11

Bump("x11-base/xorg-x11", 7, 3); CodeCleanUp(fdlibm);

x11-base/xorg-x11-7.3が入ったので,速攻でemerge.
で,x11-drivers/synapticsのbugを喰らう.
そこで困った時のbugzie,これで直る,多分. :p
bug #191924
[Emerged x11-base/xorg-x11-7.3. Eh, x11-drivers/synaptics sucks.
Kk, do dig bugzie, will fix0r soonish!!1 :p
bug #191924]

fdlibmをモニョっている.SoftFloatと合わせて,IEEE 754{,r}もチェックすれば,
あなたも明日から"ばいなりー"な浮動小数点生活をenjoy出来ます. ;)
[Poking fdlibm now. See also SoftFloat and IEEE 754{,r} for enjoy
your "binary floating-point" life. ;)]

2007/09/06

CXX.karma--;

sys-devel/gcc-4.2.0がbuggy過ぎるのとDもやりたくなってきたので,
USE=multislotでtoolchain overlayを使ってSLOT=4.1, 4.2共存の上,
4.3のalphaを突っ込んだが,ICEやらsanity check errorが止まらなーい.
やっぱりCXXはアレ気だ. :DDD
[sys-devel/gcc-4.2.0 is kinda buggy, and am interested in D.
So, now time to USE=multislot w/ toolchain overlay.
I did emerge SLOT=4.1, 4.2, and 4.3 alpha. Yay, ICE and sanity
check error floods!!1 Oh dear, CXX su^H^Hrocks!11 :DDD]

で,具体的にどれぐらいアレかと言うと,これくらい. :p
[Eh, if you'd like to see how CXX su^H^Hrocks, see this. :p]

2007/09/03

ReMeasureSLOC(&AGC_B2Fork);

例によってAGC B2ForkのSLOCを晒し上げ.
[Here is AGC B2Fork's SLOC trend to revision 124.]

前回の1.5倍位に膨れ上がっているのはテストベンチを突っ込んだから.
[Add bunch of test bench made total SLOC x1.5 bloated.]
  • revision 100辺りまでAdd draft test benches.
  • revision 120辺りまでBunch of fix for the benches.
  • revision 124で増えているのはテストベンチをまとめるラッパーを突っ込んだから.

IfGenerateStatement.karma--;

仕様なのは知ってるけど,VHDLのif-generateはなんでelseが使えないんだ? :(
[VHDL's if-generate statement kinda sux. :(]
:
:
entity FOO is
generic (
:
nDW : integer 3 to integer'high := 12;
nDELAY : integer 0 to integer'high := 2**8 - 1;
nNL : integer 3 to integer'high := 2**4 - 1;
:
);
port (
:
iCLR : in std_logic;
iDIN : in std_logic_vector(nDW-1 downto 0);
oDOUT : out std_logic_vector(nDW-1 downto 0);
:
);
end FOO;
:
architecture RTL of FOO is
:
:
constant cZEROxDW : std_logic_vector(nDW-1 downto 0) := (others => '0');
type tDMEM is array (0 to nNL-2) of std_logic_vector(nDW-1 downto 0);
signal rDMEM : tDMEM := (others => cZEROxDW);
:
:
begin
:
:
G_0FF_DELAY : if (nDELAY = 0) generate
oDOUT <= cZEROxDW when (iCLR = '1') else iDIN;
end generate;

G_1FF_DELAY : if (nDELAY = 1) generate
P_1FF_DELAY : process (iCLK)
if (iCLK'event and iCLK = '1') then
if (iCLR = '1') then
oDOUT <= cZEROxDW;
else
oDOUT <= iDIN;
end if;
end if;
end process;
end generate;

G_nFF_DELAY : if (nDELAY > 1) generate
P_nFF_DELAY : process (iCLK)
if (iCLK'event and iCLK = '1') then
nADDR <= (nADDR + 1) mod (nNL - 1)
if (iCLR = '1') then
for v in rDMEM'range loop
rDMEM(v) <= cZEROxDW;
end loop;
oDOUT <= cZEROxDW;
else
rDMEM(nADDR) <= iDIN;
oDOUT <= rDMEM(nADDR);
end if;
end if;
end process;
end generate;
:
:
end RTL;
それからModelSim XE 6.2gがこうやって書くとmultiple sourcesだと勘違いしやがる.
coverage機能がどうのこうのと言う前に嘘の警告を出さない様にしてくれ. :P
[And ModelSim XE 6.2g also sux, it'd buzz me about this code has multiple
sources, WTF. To fix wrong buzz should be given priority over to improve
coverage features, IMHO. :p]

修正: "type tDMEM us" -> "type tDMEM is"
[FIX: "type tDMEM us" -> "type tDMEM is"]

2007/08/02

MeasureSLOC(&AGC_B2Fork);

以下,AGC B2Forkの状況を晒し上げ.
[Here is AGC B2Fork's SLOC trend to revision 70.]

  • revision 5辺りまででadd FIXMEs.
  • revision 15辺りまでdelete unrelated provious' comments.
  • revision 30辺りまでexport internal generics.
  • revision 50辺りまでvarious fixes for pipeline calculations.
  • revision 50辺りでinternal statemachine rewrite.
  • revision 70辺りまでsanitize entities' name.

IsCppNewbie(&me);

ビミョーに仕事をサボりつつ,STLport関連のページとかをホゲホゲ.
個人的にC++は食わず嫌い,実際にブツを作ってみると果たしてどうなるんか少し試す事にした.
以下,メモ.
[Going on a jaunt STLport. I'm not C++ haX0r, but I don't line C++. But tasting is always not bad idea. The following is a part of diff C to C++ for me.]
  • line comment
  • default value of function's argument
  • overloaded function
  • dynamic memory
  • anonymous unions
  • class
  • constructor, destructor
  • overloading operater
  • this
  • polymorphisms
  • templates
  • name spaces
  • exception
  • type casting

単純なブツなら副作用に気を付けてCで#define使って実装してしまいそうだとか,そんな書き方は怠け過ぎだろとか思ったりするけど. :p
[Some of the aboves looks to be able to be implemented by #define macro magiX. Or looks too lazy codin' stuffs, blah blah blah... :p]

2007/07/27

agc = fork(); read(CoreConnect, &me, sizeof(ALL));

新しいRFなブツの為にAGCをfork(2).
この前のRFなブツは色々ダメダメだったのでPHY下位層はAGCも含めてかなりアレ気だったが,
今回は楽かもしれないと淡い期待をしてみる.今の所,心配なのは前回のブツの1.5倍位の
クロックで動かすつもりだという事と例のブツ一式でマンションが買える値段(ボス談)の
装置だって事だけ. :p
[Fork(2) for new RF module. The previous one really su^H^Hrocks,
it beats entire lower-than-PHY layer's consistencies includes AGC.
However, new one looks sane characteristics, IMHO. ATM, what I'm a
little worried about is it will function w/ x1.5 faster clock than previous
one and it's worth a lot of money to buy some condos. :p]

PA-RISCなブツも一通り目を通したので,ISA関連はヒトマズ終了.
次はon-chip interconnectとperipheral.
取り敢えず,CoreConnectが分かり易そうなのでコイツを読むべす. :)
[Skimed through PA-RISC's, to read something related ISA will be suspended.
Next is on-chip interconnect and peripheral. Well, CoreConnect tastes good
to me. :)]

2007/07/14

ForcedVacation(&me, 7 * WeekDay);

例のP4が終わり,その罪で今日(2007/07/14)から強制休暇一週間の刑に服役. :P
尚,今週末から来週前半は実家に戻る為,IP unreachableになります.
[Finally, I will serve 7 weekdays in forced vacation. :P
And I'd have to be IP unreachable at this weekend and few next weekdays
b/c returning to my hometown.]

以下,ここで音信不通だった間にムニャヘニャした主なモノ.
[Here is some stuffs what I was poking.]

multitalk 1.2.1のebuild及びパッチを作成
で,「パッチ作ったから次のreleaseでマージじやがれ」なEng'r'ishなメールを送信.
「そんなデカいif文はありえんので.switch文にdefaultを足すよ」
「ハードコードされているpathはディストリビューション依存だからだめ」
つーダメ出し以外は全部マージしてくれたっぽい. :)
[ebuild and patches for multitalk 1.2.1.
And I e-mail-ed to submit these patches to merge upstream w/ my Eng'r'ish.
Upstream dev replied like
"Big if statement is crazy, I'd like to add default case to the switch statement."
"To change the hard-coded path is a bit of distribution specific, I won't merge."
So, other ones are fully merged. :)]

長らくbugzieで熟成されたghdl 0.26が公式ツリーに入った.
#gentoo-ppc@irc.freenode.netでppc herdのmabiを突っついて,
「~ppcにキーワードしてーな」
と先週末位にお願いしたのにまだ~x86しかキーワードされてねーじゃん! :(
まぁ,俺様overlayの方にも残っているのでどーでもいいと言えばどうでもいいが.
[bugzie's ghdl 0.26 pwns now in official tree.
At #gentoo-ppc@irc.freenode.net, I've poked one of ppc herd, mabi
to add ~ppc to the offcial ebuild though.
That promise would be done at last weekend, but not ~ppc even now! :(
Well, but that's OK to me b/c the old one still stuffed my own overlay.]

Alpha Architechture Handbookを一通り読んだ.
PowerとMIPSのブツも読んだし,次はPA-RISC
[Alpha Architechture Handbook was pwnt.
Power and MIPS ones were already pwnt.
So next one is PA-RISC.]

他にも色々やった気がするけど,忘れた.忘れたって事は大した事ではないので割愛. :P
[Well, I can't remember other stuffs correctly. So I guess it's not so important ones. :P]

2007/06/14

MeasureSLOC(p_HardMAC);

例のP4のHardMACレポジトリのSLOCをrevisionを横軸にグラフ化.
[This is t4h HardMAC SLOC history.]

このデータを生成する為にでっち上げたスクリプトが異様に遅かったので考察する気が萎えた. :P
[Hmm, why on the earth my stupid script to generate this graph's
data is too slow? Damn it, 2 lame. :P]

2007/06/11

DoCheck(pp_graph) ? P4.karma++ : P4.karma--;

予想に反してグラフ化は半日もかからず終了,さすがsed(1p)+awk(1p),最強.
が,excelなファイルにデータをcopy'n'pasteするのに半日,なんてこった. :P
[Hmm, to convert these ton of log to graphs takes only a half of day,
thanks to damn nice sed(1p)+awk(1p). As you know, I'd have to take
another half of it for copy'n'paste to awesome excel sheets, ZOMG. :P]

明日,体裁を整えたハードコピーを納品すれば,締切に追われる仕事は無くなるハズ.
つー事で,久しぶりに#-bugsで不良社員に戻ってみる.
['Kay, all rest of TODO is making hard-copy stuffs. So, I've make me
doofus at #-bugs after long absence.]
6/11 21:21:09 hiyuh_work
yo
6/11 21:22:45 jakub
oy! :)
6/11 21:23:26 eroyf
(: !oy
6/11 21:23:39 hiyuh_work
any funny bug? :P
6/11 21:24:01 eroyf
there is that swearing bug
6/11 21:24:04 eroyf
that's quite amusing
6/11 21:24:36 jakub
haha :D
6/11 21:24:37 hiyuh_work
muhehe
6/11 21:26:41 jakub
eroyf: hmm, it's been CANTFIXed... what a surprise :D
6/11 21:26:47 eroyf
yeah
6/11 21:26:51 eroyf
amazing
6/11 21:26:52 eroyf
heh
6/11 21:26:52 eroyf
:P
6/11 21:26:56 hiyuh_work
lol
6/11 21:27:16 eroyf
it should have been STOPFILLINGRETARDEDBUGSYOUFUCKHEAD
6/11 21:27:38 jakub
oh noes, swearing in #-bugs!
6/11 21:27:44 *
jakub files a blocker bug!
6/11 21:27:45 jakub
:P
6/11 21:27:53 eroyf
hahaha
今日はoverlayでもいじるべす. :DDD
[Yay, I'll poke my overlay tonight. :DDD]

2007/06/10

wc -l log/* | tail -n 1

例のP4の試験データ取得終了.あとはコイツをグラフ化すればCLOSEだが.
['Kay, to get all test log is completed now. I can CLOSE t3h P4
when I had made some graphs w/ these logs, though.]
 ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP |  125 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 126 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 126 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_UDP | 127 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 127 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 126 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 126 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_UDP | 128 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 124 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 122 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 123 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 122 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 121 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 122 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 131 ++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT86dB_RSSI-73.0dBm_UDP | 224 +++
ttlog_BS1_SS1_CH21_16QAM1of2_TSSI13dBm_PeerATT87dB_RSSI-74.0dBm_UDP | 426 +++++++
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP | 114 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 115 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 115 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_UDP | 115 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 114 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 115 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 115 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_UDP | 115 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 113 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 111 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 110 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 111 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 112 +
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 118 ++
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 139 ++
ttlog_BS1_SS1_CH21_16QAM3of4_TSSI13dBm_PeerATT86dB_RSSI-73.0dBm_UDP | 317 +++++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT51dB_RSSI-35.8dBm_UDP | 135 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_TCP | 110 +
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT55dB_RSSI-40.0dBm_UDP | 135 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT59dB_RSSI-44.8dBm_UDP | 135 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT63dB_RSSI-49.9dBm_UDP | 132 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT65dB_RSSI-51.9dBm_UDP | 129 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT68dB_RSSI-52.8dBm_UDP | 134 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT69dB_RSSI-53.8dBm_UDP | 135 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT71dB_RSSI-56.0dBm_UDP | 134 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT73dB_RSSI-58.2dBm_UDP | 131 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT76dB_RSSI-62.3dBm_UDP | 106 +
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 104 +
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 140 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 143 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 123 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 141 ++
ttlog_BS1_SS1_CH21_BPSK3of4_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 207 +++
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP | 114 +
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 114 +
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 117 ++
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_UDP | 115 +
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 114 +
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 115 +
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 114 +
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_UDP | 114 +
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 112 +
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT77dB_RSSI-64.7dBm_UDP | 112 +
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 113 +
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 125 ++
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 126 ++
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 126 ++
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 129 ++
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 165 ++
ttlog_BS1_SS1_CH21_QPSK1of2_TSSI13dBm_PeerATT86dB_RSSI-73.0dBm_UDP | 462 +++++++
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP | 102 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 103 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 103 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT63dB_RSSI-50.3dBm_UDP | 103 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 102 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 103 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 103 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_UDP | 102 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 101 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 101 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 101 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 102 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 115 +
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 220 +++
ttlog_BS1_SS1_CH21_QPSK3of4_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 583 ++++++++++
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP | 107 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 102 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 103 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_UDP | 103 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 103 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 103 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 102 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 100 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 103 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 102 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 102 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 103 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 104 +
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 133 ++
ttlog_BS1_SS1_CH23_QPSK3of4_TSSI13dBm_PeerATT86dB_RSSI-73.0dBm_UDP | 464 +++++++
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP | 104 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 102 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 102 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_UDP | 103 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 102 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 102 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 102 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_UDP | 102 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 100 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT77dB_RSSI-64.7dBm_UDP | 100 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 103 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 103 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 102 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 103 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 105 +
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 126 ++
ttlog_BS1_SS1_CH25_QPSK3of4_TSSI13dBm_PeerATT86dB_RSSI-73.0dBm_UDP | 385 ++++++
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP | 102 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 102 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 103 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_UDP | 103 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 103 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 102 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 102 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_UDP | 103 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 101 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 101 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 101 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 101 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 101 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 103 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 116 +
ttlog_BS1_SS1_CH27_QPSK3of4_TSSI13dBm_PeerATT86dB_RSSI-73.0dBm_UDP | 329 +++++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP | 126 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 127 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 126 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_UDP | 127 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 126 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 126 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 126 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_UDP | 127 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 127 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT77dB_RSSI-64.7dBm_UDP | 129 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 128 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 127 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 127 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 127 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 128 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 138 ++
ttlog_SS1_BS1_CH21_16QAM1of2_TSSI13dBm_PeerATT86dB_RSSI-73.0dBm_UDP | 282 ++++
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP | 114 +
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 115 +
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 115 +
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_UDP | 127 ++
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 115 +
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 114 +
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 115 +
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_UDP | 115 +
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 116 +
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 115 +
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 114 +
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 116 +
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 123 ++
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 144 ++
ttlog_SS1_BS1_CH21_16QAM3of4_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 352 ++++++
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_TCP | 95 +
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_TCP | 95 +
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_TCP | 99 +
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_TCP | 97 +
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_TCP | 83 +
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_TCP | 100 +
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_TCP | 100 +
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_TCP | 100 +
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_TCP | 223 +++
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_TCP | 228 +++
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_TCP | 227 +++
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_TCP | 221 +++
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_TCP | 129 ++
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_TCP | 125 ++
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_TCP | 136 ++
ttlog_SS1_BS1_CH21_BPSK1of2_TSSI13dBm_PeerATT86dB_RSSI-73.0dBm_TCP | 302 +++++
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_TCP | 111 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP | 98 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 97 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 92 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_UDP | 96 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 97 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 96 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 94 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_UDP | 96 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 98 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 103 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 107 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 107 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 106 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 115 +
ttlog_SS1_BS1_CH21_BPSK3of4_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 185 +++
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP | 114 +
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 114 +
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 114 +
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_UDP | 114 +
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 114 +
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 114 +
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 115 +
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_UDP | 114 +
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 116 +
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT77dB_RSSI-64.7dBm_UDP | 120 ++
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 119 ++
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 120 ++
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 120 ++
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 122 ++
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 135 ++
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 304 +++++
ttlog_SS1_BS1_CH21_QPSK1of2_TSSI13dBm_PeerATT86dB_RSSI-73.0dBm_UDP | 279 ++++
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT51dB_RSSI-36.5dBm_UDP | 103 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT54dB_RSSI-39.7dBm_UDP | 104 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT59dB_RSSI-45.7dBm_UDP | 103 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT63dB_RSSI-50.7dBm_UDP | 103 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT68dB_RSSI-53.8dBm_UDP | 103 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT72dB_RSSI-58.2dBm_UDP | 103 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT74dB_RSSI-60.6dBm_UDP | 103 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT75dB_RSSI-61.8dBm_UDP | 105 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT76dB_RSSI-63.0dBm_UDP | 104 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT78dB_RSSI-65.4dBm_UDP | 104 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT80dB_RSSI-67.8dBm_UDP | 104 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT82dB_RSSI-69.1dBm_UDP | 104 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT83dB_RSSI-70.3dBm_UDP | 105 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT84dB_RSSI-71.0dBm_UDP | 112 +
ttlog_SS1_BS1_CH21_QPSK3of4_TSSI13dBm_PeerATT85dB_RSSI-72.0dBm_UDP | 244 ++++
226 files changed, 29677 insertions(+)
なんてこった.死ぬるな,これは. :DDD
[ZOMG, holly shit. :DDD]

2007/06/03

do_imp(PJITTER); relaod(p_shippo);

今日は劣悪な無線伝送路越しから確実にログファイルを回収する為の
俺様アクセス制御を再考し.結局,最大値を指定可能な疑似ジッタ付
加で良いやー,って事でサクっとインプリ完了.
月曜日にまた現地に出張って終われば良いなーとか妄想中.
[Today, I pondered a pseudo userland MAC to get some log files
over a low-link-quality wireless medium. Finally, I've implemented
it w/ maximum delay restricted pseudo-jitter retrying.
Umm, I'd have to go t3h customer's lab to adj that implementation
again.]

そうそう,このプロジェクトP4が延びに延びた為か,しっぽが再生
してしまいました. :P
['Kay. This project P4's progess delays make my shippo reload, LOL. :P]

2007/05/20

wc -l XXXXwrapper

ユーザーランドのSMEと称してPCI LB経由でHardMAC内部のレジ
スタを直にモニョれる様に改造したnet-wireless/wireless-tools
を使いまくって,sh(1p)+sed(1p)+awk(1p)なのに蝶unportable
なinitスクリプト作成中. :P
[Due to with modified net-wireless/wireless-tools which can
handle raw HardMAC register operation via PCI LB, t3h init script
as userland SME which I'm coding is really unportable even if it
only uses sh(1p), sed(1p) and awk(1p). :P]

なんか1300 SLOCを超えているんですが,罠ですか?
そうですか. :DDD
[Well, it's over 1300 physical SLOC though. I'd heve to say "O RLY?"
and "YA RLY!" :DDD]

2007/05/11

oldlibc.float.karma--; netdev.watchdog.karma--;

TSSIのRSSIへの回り込みはAGCのステートマシンをムニョって誤摩化した.
が,新たに二つ問題が発生.一つは解決済み,一つは原因を調査中.
[T3h TSSI/RSSI mixing issue, I worked around it by modifed FSM of AGC.
Meh, 2 new PITAs commin'. One of these were fixed, another one's progress
is still incestigating.]

前者は古いlibcをSH4なんつーマイナーなアーキテクチャで使用している為,
floatな演算が全部死んでいると言う悪夢.struct timevalの精度がusなので,
適当に10^6倍して整数で計算すると言うチキンな逃げもあったが,SoftFloat
をstdint.hでportしたブツでモニョった.Softfloatのライセンスに限ったモノ
でもないけれど,ライセンス云々はWTFPL以外ヨクワカンランし,詳細を
理解する気もあんまり無いので,後で叩かれない様にportしたブツはこの辺
に晒しておく.
[Former is due to old libc on SH4, a minor arch. It results nightmate of totally
invalid floating point arithmetic operation. As you know, resolution of struct
timeval is us, so in my case, to x10^6 w/ integer operation is enough to work
around this crap, how chicken though. To be no chicken is better I thought,
then I've poked it w/ SoftFloat portion w/ stdint.h. Any license is not easy to
understand its detail, except WTFPL IMHO. To prevant license violation, t3h
portion of SoftFloat is stuffed here.]

後者はSoftMACがnetdev watchdogなtransmission timeoutになる事.
多分,PCI DMA関連がハードもソフトも腐っているからだろうけど,
取り敢えず,要調査.
[Latter is a SoftMAC issue about netdev watchdog transmission faults
due to its timeout. Guess b/c PCI DMA's software/hardware suck0rz.
Anyway I'll fix ASAP.]

2007/05/08

#if DUMB_RF_CHIP #include <tssi.h> #endif

"ごーるでんうぃーく"後半,しゅーりょー.
結局,
  • 400ml献血.
    前と検査方法がちと変わっていた.

  • ALSA AOAをムニャるが,ダメっぽい.
    さすがflameeyes様,release candidateでもなんともならんぜよ. :DDD
    gcc-4.1.2で-Osなんぞかましているからかもしれん.

  • 土曜日の明け方に寝たら,日曜日の夜に起きたので,
    Overlayおよび~arch化は依然放置プレイ中. :P

つー感じでした.
[Last half of GW was over.
  • 400ml blood donated.
    T3h test method has been changed.

  • ALSA AOA still rock0rz.
    Gosh flameeyes, any release candidate won't help. :DDD
    Guess gcc-4.1.2 + -Os breaks some core stuffs?

  • Went to bed at dawn of Sat, awaked at night of Sun.
    So Overlay and ~arch-nize has little progress. :P
]

で,次期AGCのコアとなる有理数型演算マクロを土日に寝ながら妄想.
やっぱ徐算が問題,ニュートン-ラプソン法+二進約分で何とかなるかな?
[Then, I thought some idea of next AGC core, rational OPs' macro in
my sleep. Yup, DIV may be kinda PITA, Newton-Raphson method +
binary reduction may help, or?]

で,SoftMACでOOPSしない様に負荷をかけつつ,HardMACをオシロや
ロジアナでムニャへニャすると,TSSIがRSSIに回り込んでいる事が発覚.
そこで回り込みですか,まじか. :(((
[So, I've continue the HardMAC stress test w/ oscilloscope and logic
analyzer. Blah, RSSI includes TSSI... Ugh, dumb fall through, ZOMG. :(((]

2007/05/04

grabOOPS(&DMARBuf) ? DMARBuf.karma-- : DMARBuf.karma++;

"ごーるでんうぃーく"前半も終了しましたが如何がお過ごしでしょうか?
[Half of GW was over, sup ppl?]

受信側PHY下位層のゲイン調整マクロAGCの内部のステートマシンを修正.
送受信PHY下位層の直交変調復調マクロMODU/DMODUのオーバーフローを処理.
受信側PHY内部の周波数誤差補正マクロAFCのオーバーフローを処理.
送受信PHY内部のIFFT/FFTマクロのゲインを調整.
HARD_MAC/PHY間のインターフェースマクロMACIFを修正.
PCI LB/HARD_MAC間のインターフェースマクロBA_BUS_ADPを修正.
その他,色々.
[Under reception PHY, fix0rz FSM of AGC.
Under transmission/reception PHY, purge0rz OVR of MODU/DMODU.
Inside reception PHY, fix0rz OVR of AFC.
Inside transmission/reception PHY, tune0rz gain of IFFT/FFT.
Boundary of HARD_MAC/PHY, fix0rz semantics of MACIF.
Boundary of HARD_MAC, fix0rz semantics of BA_BUS_ADP.
Blah, blah, blah.]

で,やっとこさ,SoftMAC側の負荷試験が出来るなーとか思いつつ,
おもむろに"ping -f"とか"ping -s"を実行.
SoftMAC内部のPCI DMAのリングバッファがOOPSするbugが発覚.
そこでOOPSですか,まじか. :(((
[K, It's time of SoftMAC stress test.
"ping -f" and "ping -s" really sound rock.
T3h PCI DMA ring buffer sez OOPS.
Well, OOPS? O RLY? :(((]

最近,土日も関係無く仕事で,"ごーるでんうぃーく"前半をアレな感じで
フル出場してしまったので,「お前,休めよ」とボスからも"待った"を入れられる.
そこで強制休暇ですか,まじか. :DDD
[Meh, so half of GW was over now, kinda sucks.
My boss sez "U must have hols".
Well, U force me? O RLY? :DDD]

以下,"ごーるでんうぃーく"後半のTODO.
  • 献血する

  • ALSA AOAが死ぬのでムニャる

  • 放置プレイしていたOverlayをモニョる

  • ~archな先っぽでヘニャる

[Here is TODO of my last half of GW.
  • blood donation

  • Fix ALSA AOA

  • Update my Overlay

  • Play w/ ~arch
]

2007/04/29

SIGERRFREE

祝エラーフリー,BER < 10^-7 @ 16QAM 3/4. :DDD
[LOL, SIGERRFREE now. BER < 10^-7 @ 16QAM 3/4. :DDD]

が,受信側PHY下位層のCCAに自分の送信信号が引っかかる問題が発覚.
そう言えば,送信側PHY下位層のステートマシンとこの部分のステートマシン,
別々だった.エレガントに修正しようとした所,ボスに割り込みをかけられ,
モチベーション低下. :(((
[Oh wait. CCA of under-layer than RX PHY sometimes mis-detects
own TX signal as others'. Hmm, FSM in the macros of under-layer than
TX PHY is isolated from under-layer than RX PHY's, ZOMG. I'd have to
fix it ASAP though my boss interrupts my fix0rz, dunno why...]

なので月末恒例の社内飲み会でコーラをがぶ飲みして,修正は明日にして
帰って来た.ゴールデンウィーク?知らんな,そんなもん. :P
[Blah, it drains my motivation completely. So I scored Coke at where t3h
monthly NomiKai b/c mark this bug LATER. I'll fix it tomorrow.
Eh, golden week? I dunno that craps. :P]

修正:b/c typos :P
[FIX: b/c typos :P]

2007/04/27

DiffStat(pRepo, rc31, rc32);

今日の分.
入出力レイテンシを考慮して,無効な出力を禁止する処理を追加.
内部及び出力オーバフロー処理を追加して,一部ユニティゲインを調整.
firmwareにする為にISEでムニョらせて只今絶賛放置プレイ中. :P
[Here's today's one.
Reconsider input to output latencies, then make it inhibit invalid output.
Fix for internal and external overflow ceiling/flooring w/ tuning t3h
unity gain. To convert it to firmware needs to do it w/ retarded ISE craps. :P]
 bench/DUMB_RF.vhd  |   17 ++-
vhdl/AGC_CA.vhd | 6 -
vhdl/AGC_FA.vhd | 269 ++++++++++++++++++++++++++---------------------------
vhdl/DMFx8.vhd | 9 +
vhdl/IPFx8.vhd | 2
vhdl/PWRC.vhd | 32 +++---
vhdl/QDM_BPF.vhd | 10 +
vhdl/UGT.vhd | 27 ++++-
vhdl/UND_BLOCK.vhd | 124 ++++++++++++------------
vhdl/UNI_BLOCK.vhd | 90 ++++++++---------
vhdl/UNP_BLOCK.vhd | 54 ++++++----
11 files changed, 337 insertions(+), 303 deletions(-)

AGCをモニョる事が出来る人間が居ないらしいので,
何故か次のブツのAGCも担当する事になっているっぽい.
ゲイン調整をする事自体が目的ではないので行列計算が出来る位,
ハードウェア側にリソースは与えられないし,PIDはそろそろ飽きた.
昔,スライディングモード制御をヘニョった記憶があるので,
有理数型のスライディングモード制御マクロとかで. :P
[TTT, b/c there is no one who can treat AGC ATM, I'd have to do it
for next project as well. IRL, tunig RF/IF bound gain is not main
propose of the project. Yup, matrix OPs capable resource is not available
and tuning PID paramter is bit of dull. IIRC, I've poked sliding mode
control method. So rational arithmetic sliding mode control macro
is a way to go? :P]

DiffStat(pRepo, beta16, rc31);

前回からのdiffstat.
相変わらず安定しない.... :P
[Here's diffstat from previous post.
Hmm, it's kinda unstable code... :P]
 a/vhdl/CCAD.vhd            |  116 -----
a/vhdl/LOCKD.vhd | 68 ---
b/vhdl/DMFx2.vhd | 112 +++++
b/vhdl/DMFx8.vhd | 112 +++++
b/vhdl/IPFx2.vhd | 114 +++++
b/vhdl/IPFx8.vhd | 114 +++++
b/vhdl/PLSEXPI.vhd | 104 ++++
b/vhdl/QDM_BPF.vhd | 134 ++++++
b/vhdl/QM_BPF.vhd | 143 ++++++
bench/BENCH_AUGT.vhd | 56 ++
bench/BENCH_MODU_DMODU.vhd | 99 ++--
bench/BENCH_UNPID.vhd | 60 +-
bench/DUMB_RF.vhd | 143 +++++-
bench/STA.vhd | 24 -
bench/STA2STA.vhd | 12
vhdl/AAO_UGT.vhd | 120 ++---
vhdl/AGCSTM.vhd | 441 +++++++++++++------
vhdl/AGC_CA.vhd | 71 +--
vhdl/AGC_FA.vhd | 119 +++--
vhdl/AGC_NG.vhd | 292 ++++++++++---
vhdl/AUGT.vhd | 52 +-
vhdl/DC_BLOCK.vhd | 51 +-
vhdl/DMODU.vhd | 405 ++++--------------
vhdl/FFT.vhd | 20
vhdl/FPGA1.vhd | 192 ++++----
vhdl/FPGA2.vhd | 999 +++++++++++++++++++++++++++------------------
vhdl/GPS3_U301.vhd | 62 ++
vhdl/GPS3_U801.vhd | 76 ++-
vhdl/HARD_MAC.vhd | 8
vhdl/MODU.vhd | 600 ++++-----------------------
vhdl/MONSEL1.vhd | 106 ++--
vhdl/MONSEL2.vhd | 496 ++++++++++++----------
vhdl/NCDLY.vhd | 36 -
vhdl/PHY.vhd | 43 +
vhdl/PWRC.vhd | 202 +++++----
vhdl/ROUND.vhd | 76 +--
vhdl/RSSIC.vhd | 72 ++-
vhdl/RSSI_AGC.vhd | 574 ++++++++++++-------------
vhdl/RX_BBP.vhd | 405 +++++++++++-------
vhdl/SYNC_MA.vhd | 54 +-
vhdl/TX_BBP.vhd | 130 ++---
vhdl/UGT.vhd | 74 +--
vhdl/UND_BLOCK.vhd | 95 ++--
vhdl/UNI_BLOCK.vhd | 103 ++--
vhdl/UNP_BLOCK.vhd | 28 -
vhdl/VECTOR.vhd | 74 ++-
vhdl/btfly.vhd | 27 +
vhdl/outputIF.vhd | 301 ++++++++-----
48 files changed, 4517 insertions(+), 3298 deletions(-)

2007/04/15

GentooJP.NomiKai++; /* URakuChou */

ナニのついでに有楽町で飲み会.
以下,技術的有用性皆無なメモ.
  • 焼き鳥のガツは胃袋.
  • パチンコの必勝法は店員と仲良くなる事だが,賭け事はマルチンゲール也.
  • "ナガシ"の管理者とかカッコ良さ気.

[NomiKai at URakuChou.
Here is my useless memo.
  • T3h "Gatsu" means tripe in YakiTori world.
  • A winning strategy Pachinko is to get friendly the stuff, but all gamble is based on martingale.
  • Admin of "Nagasi" sounds rock0rz.
]

午前中と飲みが終わってから日付が変わるまで会社にてAGCのパラメータ調整.
-30dBmから-65dBmまで受信したっぽいが,同期検出の相関値に問題有り.
明日,と言うか今日も出社予定也. :P
[This AM and after the Nomikai, I've poke some AGC parameters.
Its reception functionality is now capable of -30dBm to -65dBm as dynamic range.
But yes, it has a PITA WRT sync timing detection's correlation function's value.
SIGNEEDSTOFIX.]

2007/03/31

DiffStat(pRepo, rc15, beta16);

あー,3/28に間に合わせる予定がー. :(((
SoftMACの方は終わっているのに,HardMACがまだまだ低品質.
で,今日までの分.
[ZOMG, 3/28, t3h date expired. :(((
SoftMAC is WORKSFORME, HardMAC is still b0rked.
Then, here's diffstat of rc15 to beta16.]
 b/vhdl/AGC_CA.vhd   |  137 +++++++++++++++++++++++++
b/vhdl/AGC_FA.vhd | 279 +++++++++++++++++++++++++++++++++++++++++++++++++++
b/vhdl/SYNC_MA.vhd | 94 +++++++++++++++++
bench/DUMB_RF.vhd | 16 ++
vhdl/AAO_UGT.vhd | 13 +-
vhdl/AGC_NG.vhd | 57 +++++++++-
vhdl/AUGT.vhd | 11 +-
vhdl/FPGA2.vhd | 37 ++++--
vhdl/NCDLY.vhd | 70 ++++++++----
vhdl/PHY.vhd | 9 +
vhdl/PWRC.vhd | 177 ++++++++++++++++++++++++--------
vhdl/RSSIC.vhd | 283 +++++++++++++++++++++++++---------------------------
vhdl/RSSI_AGC.vhd | 5
vhdl/RX_BBP.vhd | 63 ++++++-----
vhdl/RX_IOBlock.vhd | 13 +-
vhdl/TX_BBP.vhd | 21 ++-
vhdl/UGT.vhd | 76 +++++++------
vhdl/UND_BLOCK.vhd | 35 +++---
vhdl/UNI_BLOCK.vhd | 73 ++++++-------
vhdl/UNP_BLOCK.vhd | 74 +++++++------
20 files changed, 1135 insertions(+), 408 deletions(-)
土日でどれ位ヤレるのかが勝負.:P
[Sat/Sun. Am I ready to ride'on kamikaze, this spring storm. :P]

2007/03/27

DiffStat(pRepo, rc14, rc15);

ホンマモンのhot codeって,やっぱdiffだと思うのですよ,ハイ.
つー訳で,現在release candidateしまくりな例のrepositoryで約一週間分
に相当する1.0_rc15 - 1.0_rc14.
[Yup, t3h real hot code means the diff, I thought. So, here is a diffstat
from the repository between 1.0_rc14 and 1.0_rc15, it's about 1 week or so.]
 a/vhdl/AGC.vhd             |  203 -----------------
a/vhdl/PIDCONT.vhd | 265 -----------------------
a/vhdl/RSSICONV.vhd | 78 ------
b/bench/BENCH_AUGT.vhd | 106 +++++++++
b/bench/BENCH_UNPID.vhd | 231 ++++++++++++++++++++
b/vhdl/AAO_UGT.vhd | 159 +++++++++++++
b/vhdl/AGCSTM.vhd | 211 ++++++++++++++++++
b/vhdl/AGC_NG.vhd | 465 ++++++++++++++++++++++++++++++++++++++++
b/vhdl/AUGT.vhd | 195 +++++++++++++++++
b/vhdl/UND_BLOCK.vhd | 153 +++++++++++++
b/vhdl/UNI_BLOCK.vhd | 156 +++++++++++++
b/vhdl/UNP_BLOCK.vhd | 97 ++++++++
bench/BENCH_MODU_DMODU.vhd | 67 +++--
vhdl/CCAD.vhd | 91 ++++++-
vhdl/FPGA1.vhd | 28 +-
vhdl/FPGA2.vhd | 400 ++++++++++++++++++-----------------
vhdl/GPS3_U301.vhd | 61 +++--
vhdl/GPS3_U801.vhd | 62 ++---
vhdl/LOCKD.vhd | 49 ++--
vhdl/NCDLY.vhd | 59 ++---
vhdl/PWRC.vhd | 318 ++++++++-------------------
vhdl/RSSIC.vhd | 265 +++++++++++++----------
vhdl/RSSI_AGC.vhd | 512 ++++++++++++++++++++++++---------------------
vhdl/RX_BBP.vhd | 247 +++++++++++----------
vhdl/UGT.vhd | 119 ++++------
25 files changed, 2967 insertions(+), 1630 deletions(-)
んー,やっぱ思ったより少ない.
うへー,仕事してねぇー. :P
[Hmm, it's also kinda little, I expected. Well, b/c I was not so working
hard? :P]