O HAI THIS BLOG PURPZIEZ 2 B UZED AZ MAH PLESIOUS MEM. :)

2010/03/02

MeasureSLOC(&LMS); /* 2010/02 */

2月分のdiffstat.
bench/BENCH_CALCULATE_SNR_SINR.vhd |    6 
bench/BENCH_LVDS.vhd               |  485 ++++++------
bench/BENCH_S1p2SIC.vhd            |    4 
bench/BENCH_S4LLR.vhd              |  124 ++-
bench/BENCH_S5LDPCD.vhd            |  110 ++
bench/BENCH_S7RIE.vhd              |   14 
bench/METABENCH_S4LLR.vhd          |  122 +++
bench/METABENCH_S5LDPCD.vhd        |  122 +++
bench/METABENCH_S7RIE.vhd          |   26 
vhdl/ACB.vhd                       |   63 +
vhdl/ACN.vhd                       |   89 +-
vhdl/ACW.vhd                       |   64 +
vhdl/CALCULATE_SINR.vhd            |  111 +-
vhdl/CALCULATE_SNR.vhd             |  173 ++--
vhdl/CLTUNE.vhd                    |   45 -
vhdl/COMMON_TYPE_PKG.vhd           |   50 +
vhdl/CSSSTM.vhd                    |  276 -------
vhdl/DIVSR_RR.vhd                  |    4 
vhdl/EDGE_DELAY.vhd                |  163 ++++
vhdl/ESTIMATE_NOISE.vhd            |    4 
vhdl/EXPORT_F3J1.vhd               |  154 ----
vhdl/EXPORT_F4J1.vhd               |  155 ----
vhdl/EXPORT_LVDS.vhd               |  108 ++
vhdl/EXPORT_LX1_F3J2.vhd           |  162 ++++
vhdl/EXPORT_LX4_F3J1.vhd           |  176 ++++
vhdl/EXPORT_LX4_F4J1.vhd           |  177 ++++
vhdl/GSSSTM.vhd                    |  494 +++++++++++++
vhdl/IMPORT_F1J6.vhd               |  149 ---
vhdl/IMPORT_F2J4.vhd               |  148 ---
vhdl/IMPORT_LVDS.vhd               |  118 ++-
vhdl/IMPORT_LX1_F1J6.vhd           |  172 ++++
vhdl/IMPORT_LX1_F2J4.vhd           |  171 ++++
vhdl/IMPORT_LX2_F3J1.vhd           |  167 ++++
vhdl/IWSRFA.vhd                    |  624 ++++++++++++++++
vhdl/LDPCD-stub.vhd                |   96 --
vhdl/LDPCD.vhd                     |  166 ++--
vhdl/LMS_DCM.vhd                   |  216 +++++
vhdl/LMS_FORMER.vhd                | 1370 ++++++++++++++++++++++++++++++++++++
vhdl/LMS_LATTER.vhd                |  935 ++++++++++++++++++++++++
vhdl/LMS_LX1_FPGA1.vhd             | 1203 +++++++++++++++++++++++++++++++
vhdl/LMS_LX1_FPGA2.vhd             | 1404 +++++++++++++++++++++++++++++++++++++
vhdl/LMS_LX1_FPGA3.vhd             |  953 +++++++++++++++++++++++++
vhdl/LMS_LX1_FPGA4.vhd             |  727 +++++++++++++++++++
vhdl/LMS_LX3_FPGA1.vhd             |  194 +++++
vhdl/LMS_LX3_FPGA2.vhd             |  314 ++++++++
vhdl/LMS_LX3_FPGA3.vhd             |  148 +++
vhdl/LMS_LX3_FPGA4.vhd             |  119 +++
vhdl/LMS_LX_FEBE.vhd               |  841 ++++++++++++++++++++++
vhdl/PP2RIE.vhd                    |   10 
vhdl/RSTSTM.vhd                    |  213 +++++
vhdl/S0SNR.vhd                     |  398 +++++-----
vhdl/S1WINV.vhd                    |    8 
vhdl/S1p2SIC.vhd                   |   84 +-
vhdl/S3SINR.vhd                    |  286 +++----
vhdl/S4LLR.vhd                     |  100 +-
vhdl/S5LDPCD.vhd                   |  120 ++-
vhdl/S7RIE.vhd                     |   10 
vhdl/SB_MASTER.vhd                 |  783 ++++++++++++++++++++
vhdl/SB_SLAVE.vhd                  |  384 ++++++++++
vhdl/SCB.vhd                       |   59 +
vhdl/SCN.vhd                       |   73 +
vhdl/SCW.vhd                       |   60 +
vhdl/UMA_IN_SYMBOL.vhd             |   10 
vhdl/UMA_OUT_SYMBOL.vhd            |   11 
64 files changed, 14207 insertions(+), 2118 deletions(-)
ステージ化したブツのwrapperにあたるvhdl/LMS_{FORMER,LATTER}とFPGAのtop wrapperにあたるvhdl/LMS_LX1_FPGA{1,2,3,4}.vhdが無駄にデカい.vhdl/LMS_LX3_FPGA{1,2,3,4}.vhdもFPGAのtop wrapperなんだけど,使わないので中身は空っぽで小さい.

上位デザインに行くに従ってSLOCが増大する原因の一端は,entityやcomponentにオレオレrecord typeを持ってくるのがなんとなく嫌なのでportの抽象化が甘いから.自分でもinstanceをwrapする度にメンドクサさが倍増しているのを感じているんだが,どうにかしたいと思いつつ放置プレイしとる.

もう1ボード分のtop wrapperにあたるvhdl/LMS_LX2_FPGA{1,2,3,4}.vhdを書けば一通り終わりでござる. :D