[Here is snippet log of #email@example.com.
The subject is bidirectional bus.]
10/13 23:48:13 joe2371
I do not understand iobuf. What happens if I is driven to (NOT IO)?
Which input wins?
10/13 23:50:28 joe2371
Would this condition tie Vcc to ground?
10/13 23:57:15 joe2371
Do I use T to select input vs. output mode? The table I have in my
documentation does not make this clear to me.
10/14 00:08:35 joe2371
I am going to assume that the table is simply unclear and the
schematic symbol probably represents a combination of obuft with
ibuf. That would make a lot of sense, but I am surprised that the
Xilinx documentation would describe the operation the way it does.
Unless my original interpretation of the documentation is correct and
I need to use seperate ibuf and obuft components in my design. Ugh.
10/14 00:23:54 joe2371
Please look at this and tell me if I am right or wrong. Thank
10/14 00:30:40 joe2371
Hans, can you please answer my question if you have time?
I __| \______ IO
| / |
O ___/ |__|
Xilinx iobuf table:
T I IO O
1 X Z X
0 1 1 1
0 0 0 0
But I think I want this:
T I IO O
1 X 0 0
1 X 1 1
0 0 0 X
0 1 1 X
Is this what I get?
10/14 00:31:57 joe2371
I am trying to learn how to use the iobuf component and the
documentation is not clear to me.
10/14 00:33:12 joe2371
And I don't know how to test my understanding in simulation because
it is a buffer.
10/14 01:31:34 hiyuh
joe2371: did you understand...
10/14 01:31:46 hiyuh
1. "I is input from inside of FPGA, to output to IO"?
10/14 01:31:53 hiyuh
2. "O is output from outside of FPGA, to input from IO"?
10/14 01:31:55 hiyuh
3. "buffered I and unbuffered O is shared at inside of FPGA"?
10/14 01:32:33 joe2371
IO is pin side. I,O are FPGA side, right?
10/14 01:32:47 hiyuh
10/14 01:33:23 joe2371
does T select input/output mode? I mean, what happens if I is 0
but IO goes to 1?
10/14 01:35:19 joe2371
I mean, if SRAM is driving IO, how do I disable I from trying to
drive it also?
10/14 01:36:08 joe2371
Do I have to output Z to the I?
10/14 01:37:07 hiyuh
nope, T selects buffered I's state (it may not be IO's state) to 'Z'
(T = 1) or unbuffered I (T = 0).
10/14 01:38:13 joe2371
So T disables the I pin of the iobuf, but does prevent IO from
10/14 01:40:12 joe2371
I am trying to learn how to read the value of IO into the FPGA.
10/14 01:42:06 joe2371
I guess I still don't understand. And I have not been able to simulate
an iobuf to learn how it works. :-/
10/14 01:44:20 joe2371
Maybe you have answered my question already. If T=1 makes I=Z,
then hopefully O=IO.
10/14 01:45:46 joe2371
I am sorry if I do not immediately understand your explanation.
10/14 01:52:39 hiyuh
"if T <= 1, then buffered I <= 'Z' and O <= IO", "if T =
0, buffered I <= I. so O and IO <= wired(buffered I, IO comes
from as others' output)"
10/14 01:53:44 joe2371
Thank you. I think that is exactly what I want.
10/14 01:53:55 hiyuh
10/14 01:57:27 hiyuh
... so bus collision make your day, I guess. :p
10/14 01:57:35 hiyuh
10/14 01:57:36 *
10/14 01:59:37 hiyuh
FYI, to read about "I-BEFORE" and "OUT-AFTER" for ucf files' timing
constrain would be useful.
10/14 01:59:53 hiyuh
10/14 02:00:31 joe2371
oh, no. This means "O and IO <= wired(I, IO comes from SRAM)"
means two inputs on same bus. That is not what I want, of course.
10/14 02:01:34 hiyuh
10/14 02:02:13 joe2371
"assign IO = I and assign IO = SRAM-output" at the same time is not
what I want. Does this mean I cannot use iobuf for my design?
10/14 02:03:05 joe2371
I will look for "I-BEFORE" and "OUT-AFTER" for ucf files.
10/14 02:07:54 hiyuh
so, to keep IO <= 'Z' w/ T = '1' as neutral. when you really want
to output via IOBUF, make sure SRAM is input-state before output
via IOBUF. when others, you should think SRAM may be output-state.
10/14 02:08:53 joe2371
oh, I see.
10/14 02:08:56 hiyuh
otherwise, bus collisoin makes your day. :p