agc = fork(); read(CoreConnect, &me, sizeof(ALL));

新しいRFなブツの為にAGCをfork(2)．
この前のRFなブツは色々ダメダメだったのでPHY下位層はAGCも含めてかなりアレ気だったが，
今回は楽かもしれないと淡い期待をしてみる．今の所，心配なのは前回のブツの1.5倍位の
クロックで動かすつもりだという事と例のブツ一式でマンションが買える値段（ボス談）の
装置だって事だけ． :p
[Fork(2) for new RF module. The previous one really su^H^Hrocks,
it beats entire lower-than-PHY layer's consistencies includes AGC.
However, new one looks sane characteristics, IMHO. ATM, what I'm a
little worried about is it will function w/ x1.5 faster clock than previous
one and it's worth a lot of money to buy some condos. :p]

PA-RISCなブツも一通り目を通したので，ISA関連はヒトマズ終了．
次はon-chip interconnectとperipheral．
取り敢えず，CoreConnectが分かり易そうなのでコイツを読むべす． :)
[Skimed through PA-RISC's, to read something related ISA will be suspended.
Next is on-chip interconnect and peripheral. Well, CoreConnect tastes good
to me. :)]