O HAI THIS BLOG PURPZIEZ 2 B UZED AZ MAH PLESIOUS MEM. :)

2009/07/26

doFlame(&numeric_std);

#vhdlのnumeric_stdな猿共と再度flameしてみた. :P
07/25 21:03:01 hiyuh
hmm
07/25 21:03:31 hiyuh
i did migrate std_logic_arith to numeric_std on my current proj.
07/25 21:04:06 hiyuh
but i think numeric_std still sux in my style/use.
07/25 21:04:49 hiyuh
anybody have good example code which use numeric_std elegant?
07/25 21:04:56 hiyuh
s/use/uses/
07/25 21:06:39 hiyuh
MatthiasM, NULL[0] ^^ :)
07/25 21:06:44 MatthiasM
:)
07/25 21:07:25 MatthiasM
there is not much to say - if you have a signal/variable which is
used in computations, then declare it as (un)signed
07/25 21:07:29 Sordran_
hiyuh:
http://www.dz.ee.ethz.ch/en/information/hdl-help/vhdl-sources.html
07/25 21:12:00 hiyuh
hmm
07/25 22:17:16 bpadalino
hiyuh: yeah, what's the issue ?
07/25 22:21:23 hiyuh
one of issues I hate numeric_std is it breaks port compatibilty.
07/25 22:21:26 hiyuh
b/c all of mine was std_logic, std_logic_vector, range constrained
integer or custom type.
07/25 22:22:22 hiyuh
i know inner std_logic_vector() wrapping makes it compatible,
but it's very eyesore.
07/25 22:24:00 bpadalino
so don't convert to slv at the port level
07/25 22:24:08 bpadalino
if it's an unsigned number - keep it an unsigned number
07/25 22:24:14 bpadalino
preserve context as much as possible
07/25 22:28:13 hiyuh
nope, for lazy simulation, I did input ascending/descending number
to data port. it's data, not unsigned/signed.
07/25 22:31:26 hiyuh
and another one I hate is to declare unsigned/signed signal/variable
and computing w/o unsigned()/signed().
07/25 22:32:21 bpadalino
you can always overload your functions .. and add your own package
07/25 22:33:12 hiyuh
if you recommend overloading, i won't use numeric_std TBH.
07/25 22:33:26 hiyuh
it's pain to me atm.
07/25 22:33:44 bpadalino
numeric_std removes ambiguity from your code - if you find it to
be a pain, then live with the ambiguity
07/25 22:34:40 hiyuh
then plz show me that ambiguity which comes from std_logic_arith?
07/25 22:35:56 bpadalino
a <= b + x"abcd"
07/25 22:35:58 bpadalino
what did i just do
07/25 22:38:27 hiyuh
every time I compute std_logic_vector, I always do it w/ explicit
unsigned()/signed(). and also I don't use hexadecimal/binary
presented std_logic_vector for any computation.
07/25 22:39:45 bpadalino
congrats - but it doesn't remove the ambiguity that can happen
07/25 22:39:47 bpadalino
use whatever you want
07/25 22:41:17 hiyuh
promote me more, why that doesn't remove the ambiguity?
07/25 22:42:45 bpadalino
because you can still abuse it
07/25 22:44:38 hiyuh
hmm
07/25 22:48:17 bpadalino
i understand numeric_std makes your code look "ugly" if you do a
lot of casting
07/25 22:48:47 bpadalino
answer is to do less casting
07/25 22:54:48 hiyuh
I'd like to say trivial explicit casting is not eyesore to me.
07/25 22:54:57 hiyuh
atm i don't like numeric_std's implicit type guessing to compute.
07/25 22:55:02 hiyuh
b/c to see which function is used, it needs to see their
declarations.
07/25 22:55:49 bpadalino
guessing ?
07/25 22:56:39 hiyuh
signal a : signed; signal b : signed; signal c : signed; ... some
line of code ... c <= a + b; -- numeric_std use.
07/25 22:59:10 hiyuh
+ of "a + b" is "signed + signed". but to figure out that, it needs
to see their declaration.
07/25 22:59:40 MatthiasM
the issue why code may look ugly is that it is not cleanly designed -
eg when writing software you have to carefully define the types of
variables, parameters and return values
07/25 23:00:05 bpadalino
how is that not any different than how it would happen with
std_logic_arith ?
07/25 23:01:16 hiyuh
my std_logic_arith use looks like,
07/25 23:01:17 hiyuh
signal a : std_logic_vector; signal b : std_logic_vector; signal
c : std_logic_vector; ... some lines of code ... c <= signed(a)
+ signed(b);
07/25 23:02:00 bpadalino
is a or b or c a signed or unsigned number ?
07/25 23:02:05 bpadalino
wow, that's all sorts of crazy
07/25 23:03:19 bpadalino
nothing stops you from going c <= unsigned(a) + signed(b) ;
07/25 23:03:24 bpadalino
so it's really just a bunch of bits
07/25 23:04:22 hiyuh
I mean arg type and computation is one set.
07/25 23:04:26 hiyuh
signal a : signed; signal b : signed; signal c : signed;
... some line of code ... c <= signed(std_logic_vector(a)) +
unsigned(std_logic_vector(b));
07/25 23:04:41 hiyuh
is it valid for numeric_std?
07/25 23:04:56 bpadalino
yes
07/25 23:05:24 hiyuh
if so, declaration is not for force to use proper computation.
07/25 23:06:07 bpadalino
if i saw unsigned(std_logic_vector(b)) in a code review, i think
my red flags would go up
07/25 23:06:18 bpadalino
but if i saw signed(b) - i wouldn't think twice
07/25 23:06:40 bpadalino
numeric_std doesn't stop you from being an idiot - it just makes
it harder
07/25 23:07:17 hiyuh
yeah
07/25 23:08:33 bpadalino
they're supposed to be a set of functions which help you
07/25 23:08:42 bpadalino
if you don't find them helpful, don't use them
07/25 23:09:22 hiyuh
but if i stick std_logic_arith, MatthiasM will bitch me. :P
07/25 23:09:52 MatthiasM
sure
07/25 23:14:30 bpadalino
so learn to quit writing ambiguous code
07/25 23:16:09 hiyuh
signal a : signed; signal b : signed; signal c : signed; ... some
line of code ... c <= a + b; -- (1)
07/25 23:16:12 hiyuh
signal a : std_logic_vector; signal b : std_logic_vector; signal
c : std_logic_vector; ... some lines of code ... c <= signed(a) +
signed(b); -- (2)
07/25 23:16:54 hiyuh
to review code, (1) needs to check declaration and computation. (2)
needs to check computation only.
07/25 23:17:27 hiyuh
that's why I hate numeric_std atm.
07/25 23:17:30 bpadalino
d <= unsigned(a) + signed(b) ;
07/25 23:17:45 bpadalino
does not enforce that a is a signed type
07/25 23:18:07 bpadalino
if you want to be loose, and not have matthiam bitch at you -
use verilog
07/25 23:18:15 bpadalino
but in a strongly typed language, learn to deal with it
07/25 23:18:17 MatthiasM
hiyuh: with (2) you have to check that a is used in the same way
everywhere
07/25 23:18:52 bpadalino
also - if you pass a out a port as a slv, there is no guarantee it
will be maintained as that representation later on
07/25 23:19:00 bpadalino
which only causes more confusion
07/25 23:19:53 MatthiasM
the only place where you should keep using SLV is at the top level -
because post fitting timing simulation is loosing the port type -
and then your testbench doesn't work anymore :(
07/25 23:20:15 bpadalino
:(
07/25 23:21:16 hiyuh
MatthiasM: (1) is same b/c think that crappy code like,
07/25 23:21:21 hiyuh
signal a : signed; signal b : signed; signal c : signed;
... some line of code ... c <= signed(std_logic_vector(a)) +
unsigned(std_logic_vector(b)); -- (3)
07/25 23:21:39 bpadalino
hiyuh, if you want to shoot yourself in the foot easier, i think
aliases might make your life more hellish
07/25 23:22:03 MatthiasM
hiyuh: if I would have to review your code and it contains such a
thing - you would rewrite it again
07/25 23:27:21 hiyuh
bpadalino: if you declare port as signed/unsigned, it doesn't force
to use that type. b/c there is idiot casts.
07/25 23:27:48 bpadalino
hiyuh, like i said - you can always be an idiot, numeric_std just
makes it harder
07/25 23:28:42 hiyuh
and it does also analyze harder. that's why I hate numeric_std.
07/25 23:30:19 hiyuh
if declaration can not force proper type use, i think type in
declaration is redundant info.
07/25 23:31:24 hiyuh
if using numeric_std doesn't allow any casting, it make sense.
07/25 23:31:36 hiyuh
but it's not.
07/25 23:32:04 MatthiasM
hiyuh: well - do what you want - but spot anoyng everyone with your
bad design
07/25 23:32:11 MatthiasM
*stop
07/25 23:34:27 hiyuh
annoy?
07/25 23:34:29 hiyuh
I'm really talking in technical view.
07/25 23:34:31 bpadalino
you know, no reason to even use std_logic_vectors since we're just
going down to bits ...
07/25 23:34:37 bpadalino
so lets just do std_logic
07/25 23:35:52 bpadalino
hiyuh, you want to be stuck in a type you can't get out of ?
07/25 23:36:05 bpadalino
or would you rather be forced to think about the computation you're
doing ?
07/25 23:46:51 hiyuh
well. you're talking about bit to std_logic migration?
07/25 23:47:12 hiyuh
you mean it's same wrt migration std_logic_arith to numeric_std?
07/25 23:48:09 hiyuh
btw sorry for my bad english.
07/25 23:48:51 bpadalino
i am saying you can use whatever you like - but your arguments
are weak
07/25 23:49:07 hiyuh
hmm
07/25 23:50:02 hiyuh
maybe, it's b/c i have little experience w/ numeric_std.
07/25 23:50:50 hiyuh
so I should read more elegant std_logic_arith to numeric_std
migration examples.
07/25 23:51:08 bpadalino
there's nothing elegant about it
07/25 23:51:26 hiyuh
why?
07/25 23:51:51 bpadalino
the way you're doing it, trust me - there's no elegant way about it
07/25 23:51:59 bpadalino
all your base types are slv ..
07/25 23:52:06 bpadalino
so you will have to cast everything
07/25 23:52:20 bpadalino
first to get to something workable, then back to your slv base type
07/25 23:52:35 bpadalino
you're really doing a lot of work to lose intent and context of
the code
07/25 23:52:54 bpadalino
lets write a c program where all we use are char's .. and cast
everything when we need it to be something else
07/25 23:53:11 hiyuh
nope, I cloned my proj for the migration test. I'm using mercurial.
07/25 23:53:43 bpadalino
scm has nothing to do with elegance or porting poorly written code
to using numeric_std
07/25 23:59:17 hiyuh
well, I've just done to migrate std_logic_arith to numeric_std
already.
07/26 00:00:14 hiyuh
it takes about 1 hour or so. but i think it's ugly.
07/26 00:01:55 hiyuh
to motivate myself more, I'm talking here.
07/26 00:02:54 hiyuh
I beleive my code base is not poor you think.
07/26 00:02:57 hiyuh
it works w/ 2 boards which each one has 4 virtex4.
07/26 00:03:08 hiyuh
all ones are written in two-process method.
07/26 00:08:03 bpadalino
sounds great when you're the only person working on the code
07/26 00:08:04 bpadalino
keep it up
07/26 00:10:08 hiyuh
yup, it was coded by me only.
07/26 00:29:23 bpadalino
if you're the only person, write it any way you want
07/26 00:34:19 hiyuh
ok, thank you for taking your time.

取り敢えず,再確認出来た事としては技術的な話をしている時に"stop annoying"とか"trust me"とかふざけた事を言う奴の意見は聴くに値しないと言う事だな.
結局,suckless.orgのstyle guideが言う様にconsistencyが重要だとすれば,自分のstyleと相容れないpackageを無理に使う事はないって事になるのかな?
つー訳で,やっぱり私は当分の間はnumeric_stdにmigrateする事はありません. :P

2009/07/19

doFlame(&std_logic_arith);

取り敢えず,KMSがmodeset=0で動く様になったと思ったら#vhdlにnumeric_stdな猿が居たのでflameしてみた. :P
07/19 02:35:22 jv
MatthiasM: Why is logic_arith so pervasive?
07/19 02:35:41 MatthiasM
?
07/19 02:46:31 jv
MatthiasM: why people keep using std_logic_artih
07/19 02:46:56 MatthiasM
maybe because neither Xilinx or Altera updated their language
templates

07/19 03:27:50 hiyuh
jv: MatthiasM: promote me numeric_std more. then I'll switch from
sticking std_logic_arith.
07/19 03:28:21 MatthiasM
hiyuh: simple - no help for everyone who uses std_logic_arith :P
07/19 03:28:40 hiyuh
ha
07/19 03:30:21 NULL[0]
we need to open a new channel for that: #vhdl-93
07/19 03:30:55 MatthiasM
or #vhdl-only-for-std_numeric-users
07/19 03:31:12 hiyuh
there is no system doesn't support std_logic_arith and
numeric_std. monkey is just saying "it's t3h standard".
07/19 03:32:05 NULL[0]
a 15 years old tool supporting only vhdl-87 will not support
numeric_std ;p
07/19 03:32:35 hiyuh
no, that kind of craps are not system anymore. :p
07/19 03:36:29 hiyuh
anyway, vhdl-93/2002 doesn't bother to use std_logic_arith, iirc.
07/19 03:36:58 NULL[0]
because it is not necessary anymore
07/19 03:39:00 hiyuh
so plz, promote me in technical view. numeric_std is different from
std_logic_arith. why I should migrate?
07/19 03:39:15 hiyuh
s/I should/should I/
07/19 03:39:50 NULL[0]
one is a standard the other one a de facto standard that will
hopefully be deprecated soon ;)
07/19 03:40:27 NULL[0]
unfortunately it will never happen ;/
07/19 03:41:05 hiyuh
yup, de facto standard won't be deprecated. b/c monky is just saying
"it's t3h standard".
07/19 03:41:20 hiyuh
so plz promote me more.
07/19 03:42:07 NULL[0]
I don't really care :p, I have seen only 1 stupid case combining
std_logic_signed and std_logic_unsigned which broke the code
07/19 03:43:05 NULL[0]
something impossible with numeric_std ;)
07/19 03:43:12 NULL[0]
alone
07/19 03:44:43 hiyuh
std_logic_arith is not std_logic_{signed,unsigned}.
07/19 03:44:45 hiyuh
mixing them does overload some functions in current vhdl standard,
it just makes noobs confuse.
07/19 03:45:17 NULL[0]
std_logic_(un)signed is part of the synopsys libraries like
std_logic_arith
07/19 03:45:50 hiyuh
nope, they are separated, iirc.
07/19 03:46:08 NULL[0]
library IEEE;
07/19 03:46:08 NULL[0]
use IEEE.std_logic_1164.all;
07/19 03:46:08 NULL[0]
use IEEE.std_logic_arith.all;
07/19 03:46:24 NULL[0]
that's the beginning of std_logic_signed
07/19 03:46:37 NULL[0]
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
07/19 03:49:10 hiyuh
http://pastebin.com/m545ddbec
07/19 03:49:54 NULL[0]
and ?
07/19 03:51:13 hiyuh
synopsys/std_logic_arith.vhdl has only "use ieee.std_logic_1164.all;"
07/19 03:51:23 hiyuh
so, they are separated.
07/19 03:51:40 NULL[0]
std_logic_(un)signed is a wrapper applied on std_logic_arith
07/19 03:52:43 hiyuh
heh
07/19 03:53:00 hiyuh
but i don't use std_logic_unsigned/std_logic_signed to avoid overload
problem.
07/19 03:54:34 NULL[0]
std_logic_arith and numeric_std have more or less the same
functionalities, so there is no reason to use the library which is
not standard in newer code
07/19 03:55:24 hiyuh
again, plz promote me more.
07/19 03:55:37 hiyuh
in technical view.
07/19 03:56:05 hiyuh
std_logic_arith and numeric_std have more or less the same
functionalities, so there is no reason to migrate the library which
is not de facto standard.
07/19 03:57:09 hiyuh
NULL[0]: so what you said is "in technical"?
07/19 03:57:22 hiyuh
i don't think so.
07/19 03:57:28 MatthiasM
hiyuh: numeric_std has resize
07/19 03:57:51 MatthiasM
and shift_left/right with warnings when the numerical value changed
because of overflow
07/19 03:58:01 hiyuh
heh
07/19 03:58:23 MatthiasM
eg resize(to_unsigned(10, 4), 3) gives a warning in simulation
07/19 03:58:45 MatthiasM
but resize(to_unsigned(10, 5), 4) is ok

07/19 04:02:52 hiyuh
yo, |fred| :)
07/19 04:03:14 |fred|
perfect timing to disappear ;o)
07/19 04:03:22 hiyuh
lol
07/19 04:33:26 |fred|
hiyuh: I have actually right now to follow a guideline forbidding
numeric_std :)
07/19 04:34:00 hiyuh
lol
07/19 04:34:59 hiyuh
k, i'll switch to numeric_std at next proj.
07/19 04:35:01 hiyuh
:D

他人に新しいモノをすすめる時には,trivialでtechnicalな利点を根拠に持たないとダメだと思う.
"it's t3h standard!!1"は"but ITJUSTWORKS(tm)"で一蹴される阿呆に共通する特徴.
んな事を言ったって,我らが仮想敵なボスの無意味に保守的な態度に対向出来る訳無ぇだろよ,カスが.
でも,実を言うとstd_logic_arithに気に入らない所もあるので,今度から numeric_stdを使ってみっかな.
std_logic_arithにしがみついているのは,#vhdlでは少数派の様だし. :P

2009/07/15

migrate2KMS(&nouveau); Firmware.karma--;

nouveauがKMSに移行しろと言うのでゴニョる.
見ての通り大変な事になっとるので,もう少し弄る予定ナリよ. :DDD


一ヶ月程ハマっていた問題の原因らしきモノが発覚.
結論から言うと,on-chip firmwareが腐っている臭い.
取り敢えず,コードに罵詈雑言を埋め込んでおこう. :P

勿論,スタイルはtwo-process手法をベースにmultiple CDCとlegacy/tech-specific blobに対応.
問題は抽象化レベルが高くて理解出来る人が少ない事か?

2009/07/09

addSpice(&OSS, aBUG);


NWCCの中の人とのメールの一部.

バグってんのはバグってんのでおもしろいモノだと思う.
でも,faultless golden codeを書いてやろうとする気概は常に持ちたいもんだ.
特に仕事でコード書いている時は"ぷろふぇっしょなる"として扱われている事を念頭において欲しいよなぁ.

最近,会社でVHDLを教える機会があって,アレなコードを見る度に罵詈雑言(?)を吐く不良社員ぶりを発揮していたのだが,そうやって温室培養し過ぎると,負の遺産であるウンコなコードに耐性が無くなってしまうと言う弱点もある事に気づいた.
大人の事情もあるし,そう言う腐りかけの生ゴミにあんまり手を触れない様に,異臭のするカビがこっちにも移ってしまわない様に,巧く扱う方法も教えていかねばならんね.
なんとこの世は{生,逝}き難い事か!!1 :P

2009/07/03

MeasureSLOC(&AL9); /* 2009/06 */

AでLで9なdiffstat,6月分.
[diffstat for AL9, for 2009/06.]
 bench/BENCH_AFIFO.vhd         |    2 
bench/BENCH_BCMUX.vhd | 2
bench/BENCH_CLDPCDOP.vhd | 9
bench/BENCH_LDPCDDB.vhd | 126 +-
bench/BENCH_LDPCTX.vhd | 720 --------------
bench/BENCH_LDPCTX2LDPCRX.vhd | 1846 +++++++++++++++++++++++++++++++++++++
bench/BENCH_S2BER_IF.vhd | 194 +++
bench/BENCH_SB.vhd | 345 ++++---
bench/BENCH_SFIFO.vhd | 2
bench/BENCH_XQUEUE.vhd | 2
bench/LDPCRX_MEM.vhd | 187 +++
bench/LDPCTX_MEM.vhd | 4
stim/STIM_TX_DATA_CARR.vhd | 2
vhdl/BCBOOL.vhd | 172 +++
vhdl/BCMUX.vhd | 160 +++
vhdl/BER_IF_CLK.vhd | 26
vhdl/BER_IF_REG.vhd | 94 +
vhdl/CLDPCDOP.vhd | 3
vhdl/COS_VLSX4_MEM.vhd | 838 +++++++++++++++++
vhdl/ELDPCDII.vhd | 202 ----
vhdl/ELDPCDIP.vhd | 204 ++++
vhdl/FP1_LDPCRX.vhd | 2004 ++++++++++++++++++++++-------------------
vhdl/FP1_LDPCTX.vhd | 79 +
vhdl/FP2_LDPCRX.vhd | 2052 ++++++++++++++++++++++++------------------
vhdl/FP2_LDPCTX.vhd | 79 +
vhdl/FP3_LDPCRX.vhd | 489 ++++++----
vhdl/FP3_LDPCTX.vhd | 6
vhdl/FP4_LDPCRX.vhd | 471 ++++++---
vhdl/FP4_LDPCTX.vhd | 6
vhdl/HD2BO.vhd | 11
vhdl/LEDIND.vhd | 180 +++
vhdl/LLR2SC.vhd | 31
vhdl/PSQUASH.vhd | 22
vhdl/RX_LX_FEBE.vhd | 92 +
vhdl/S2BER_IF.vhd | 22
vhdl/SBSSBDD.vhd | 19
vhdl/SB_MASTER.vhd | 145 ++
vhdl/SB_SLAVE.vhd | 45
vhdl/SELDPCDIIM.vhd | 571 -----------
vhdl/SELDPCDIPM.vhd | 845 +++++++++++++++++
vhdl/TSR_CLK.vhd | 32
vhdl/TX_SX_FEBE.vhd | 34
vhdl/XDPRAM.vhd | 2
vhdl/XDYNSR.vhd | 2
vhdl/XQUEUE.vhd | 2
vhdl/XSPRAM.vhd | 2
vhdl/XSPSR.vhd | 2
vhdl/XSSSR.vhd | 2
48 files changed, 8288 insertions(+), 4099 deletions(-)

やっぱ,10kSLOC逝ってないZE!!1 :DDD
受信側のtop wrapperをrewriteしたのが一番大変だったかのぅ.
[ZOMG, under 10kSLOC AGAIN!!1 :DDD
Rewriting RX's top wrappers were rather big to me.]