downstream = dup(upstream);

s9fesのさきっぽを追っかけてるらしいdebianな人が「オレのとdupってるぜ！！1」とか言うのでその返事．

きっと親切心でメールをくれたんだと思うんだけど，オレはさきっぽを追っかける事自体が目的みたいなもんだからdupしてても一向に構わんのだけどなぁ．
結局upstreamの中の人が気に入ればdownstreamのchangesetはupstreamにmergeされて，結果全てのdownstreamに還元される訳だし，DSCMってそう言う為のモノじゃねぇの？

つーか，なんでみんなgit使ってんだよ！！1 :DDD

Me -= Blood; Me +=Coffee; Me += GyouZa;

高専時代の知り合いから電話があった．
オレと違って大学に編入した後で修士まで行ったらしく，しかもオレの今の仕事の分野に近いトコロをゴニョっていた様で妙に話が合って蝶意外．

が，メインはそっちじゃなくて，高尚なものではないけど抽象的な人生相談(?)の様なモノだった．
例の如く不況の煽りを受けて修士を出てから就職した会社のある部門が無くなるそうで．
「オレはエラくもないし，職は斡旋出来ないぜー」とか言ったら，もう幾つか内定は貰っているが，いい機会だから色々考えたいんだとか．
で，高専時代でもオタク全開だったオレが今は何をやらかしているのかとか聞きたかったらしい．
ふむふむ．．．ぬるへそ，ぬるへそ．．．
．．．って，オタクのまんまに決まってんじゃん，変わりゃしねぇよ． :DDD

つー訳で，オレはヒキコモリなハズなんだが，土日連続で外出すると言う異例の事態に．
駅で待ち合わせをしている間のヒマつぶしに献血して，合流してから"どとぉる"なコーヒーと餃子メインの店のメシをゴチになってきた．
オレの話が参考になったかどうか分からんけど，彼はオレよりずっと英語出来るし，スゲェイケメンなので大丈夫じゃね？ :DDD

別れ際，「今度就職祝いしてくれー」とか言ってた．
今日のお返しにメシくらいおごってやるさ．
まぁ，頑張れや． :)

HikiKomori | ~HikiKomori

会社に案内が来てて，ボスが「暇なら行けば？」みたいな事を言っていたので，俺はひきこもりなはずなんだが，今日はNHK放送研究所の技研公開に行ってきた．
休日なので一般の人が蝶いっぱい．

見栄えのするブツの方に人が集まってたけど，仕事でお手伝いさせてもらったブツの展示をメインに見てきた．
アンテナの受信信号を並列に記録するHDDレコーダのお化けを拵えてリアルタイム復調してた，地味にすげぇ． :DDD

それにしてもあの辺は雰囲気がおしゃれ(?)過ぎて，なんか落ち着かない．
んー，どうしたもんかなぁ．

USE=-gold emerge sys-devel/binutils

　ボブ「やぁ，ジョニー，聞いてくれよ．」
ジョニー「なんだい，ボブ．」
　　ボブ「IUSE=goldなsys-devel/binutilsを見つけたので，chrootもせずにemergeしたんだ．」
ジョニー「へぇ，それはなんともricerらしいじゃないか．」
　　ボブ「だけどさ，続いてemergeしようとしたsys-apps/shadowのeconfがコケるんだ．」
ジョニー「それはまたどうして？」
　　ボブ「僕も変だなと思って，手元の自分のCのプログラムをコンパイルしてみたんだ．」
ジョニー「それで？」
　　ボブ「なんと何もコンパイル出来なくなってたんだよ！」
ジョニー「なんてこった！」
　　ボブ「慌ててUSE=-goldでsys-devel/binutilsをemergeしなおそうとしたんだけど．」
ジョニー「ダメだったと．」
　　ボブ「そうなんだ．」
ジョニー「なるほど．」
　　ボブ「なぁ，ジョニー，どうしたいいと思う？」
ジョニー「そんな時はricerなオレ達の強い味方，tinderbox.dev.gentoo.orgの出番さ．」
　　ボブ「何だいそれは？」
ジョニー「systemでstableなブツやクロスコンパイラのバイナリなんかを提供しているトコさ．」
　　ボブ「へぇ，普段自前でしかコンパイルしないから知らなかったよ．」
ジョニー「で，コイツをPORTAGE_BINHOSTで指定して-gKでemergeすれば良いんじゃないかな？」
　　ボブ「具体的には僕の場合はどうやるんだい？」
ジョニー「君はなぜかppc32だったよね？」
　　ボブ「うん，x86が嫌いだからね．」
ジョニー「ならこうさ！」

PORTAGE_BINHOST=http://tinderbox.dev.gentoo.org/default-linux/powerpc/ppc32 \
    emerge -gK =sys-devel/binutils-2.18-r3

　　ボブ「へぇ，いつもemergeするのとあんまり変わらないね．」
ジョニー「これで少し古いけどsys-devel/binutilsは治ったハズだよ．」
　　ボブ「なるほど，これで改めてUSE=-goldでsys-devel/binutilsをemergeすれば良いんだね！」
ジョニー「そうさ，簡単だろ？」
　　ボブ「ああ，やっぱりGentooは最高だね！」

Barcamp.Tokyo[2009] = BenTou + Curry;

waitingだったんだけど，「それでも大丈夫だから来い」みたいなことを言われたのでBarcamp Tokyo 2009に行ってきた．
TLUG並に外国人参加率が高くて，そこら中でネイティブっぽい人達の英語が炸裂してて，俺もPowerBoook弄ってまともに話を聞いていない事も相俟って当社比2倍で訳分からんかった．

あるbrainstormingで「barcampの日本人参加率を上げようぜ」みたいなネタが出て，ありえないぐらいマシンガンかましている人がいたが，正直何を言いたいのかさっぱり聞き取れんかった．
これは新手のプレイだね，間違い無い．

つーか，良く考えたら何で日本人参加率を上げたいんだろう？
彼らが都合の良い英語をプロトコルに使って，実のある話が出来れば日本人参加率が低くても良さそうなもんだけどなぁ．
仮に日本語でのプレゼンやら質疑応答を許可したとしても，そこら中でマシンガンかましているのが大多数だったら，普段英語なんか使う機会が殆ど無い日本人の参加率が上がる訳無ぇだろ，とかここではdisってみる．
少なくとも俺には「郷には入れば郷に従え」ってのが強迫観念みたいに頭から離れんよ．

言い訳しておくと，俺はコードのコメントは悉く英語だし，情報が英語で書かれていても知りたい情報なら読むし，IRCで1337 speakでフザケてたりするけど，耳と口は英語化してないんだよなぁ．
大抵の日本人はコードのコメントは日本語だし，情報が英語で書かれていたら読むのを躊躇うし，IRCで1337 speakなんかしないので，もっと英語化はしていないと思うんよ．

だから，向こうがマシンガンを捨ててカタナに装備を変えるか，こっちがカタナを捨ててマシンガンを装備するかのどちらかをしないと同じ戦場でまともに戦えない．
で，不味い事にマシンガンの方が戦力的に見て圧倒的に有利と言う現状がある訳で，極一部のサムライはカタナを捨ててマシンガンを装備するけど，残りの人達はカタナを持ったまま突撃するか，出島を作って鎖国するか，カタナを捨てて畑を耕してる．

brainstormingは基本的に否定/批判を排したブツだから，その場でどうこうってのはやらなかったし，する気も無かったけど，あそこでマシンガンぶっ放してた人達は最初からマシンガンだけしか装備していなかったとか，ただ単にカタナで斬り合った経験が無いだけだったりしねぇ？
それを一方的に「fair playじゃねぇ！！1」とか言う気は無いし，俺はカタナが結構好きだから別に構わないけど，同じ戦場でまともに戦う事を一番に望んでいるなら，マシンガンをぶっ放してた方はカタナも装備してみようとか，カタナでしか斬り合いした事が無いならマシンガンでもぶっ放してみようとか，っつー言う気概くらいはあっても良いと思うんだよね．

そう言う意味では拙い日本語でコミュニケーションをしようとしてくれるガイジンさんにはとても感謝したいし，俺のbr0ken Englishでも良いなら受け答えしてあげたいと思う．
ま，中々巧く話が進まない所もあってもどかしいけど，だがそれが良い． :)

ああ，そうそう．昼飯の弁当と夕食のカレーはタダ飯だったのでこんなタイトルになってます．深い意味はありません． :DDD

wm.lineage->next();

graphvizがタルくなったので，inkscapeを乗り換えた．
んで，色着けて線が交わらない様にしてみた． :)
SVGはここに晒しておこう．
[using inkscape instead of graphviz, then colorize and flatten. :)
want SVG? here it is.]

線はそれなりに関連があるって事で，必ずしもforkやrewriteを意味する分けでは無かったりする．
タイル型WMでないモノも入っていたり，そもそもWMじゃないモノも入っているがそれなりに意味がある．
[lines just indicate their relation, not only fork/rewrite.
There is some non-tiling WMs, more over few ones are not WM.
But they're worth to mention for explaining about recent GUI improvement for experienced users.]

あとはmultitalkの資料が間に合うかどうかだな． :p
[hmm, making presentation 2D map by multitalk? oh well. :P]

TLUG.NomiKai++; synthSound(&hardware);

TLUGに行ってきた．
BarCamp-Tokyo2009の中の人がHypertextについて話してたのと，XMLとSQLの香りがするsemantic webの話だった．
皆さんはレイヤが高いですな，あいかわらず． :)
飲み会/二次会ではshojiさんのSunオフレコ話とかJARIさん（北欧のイケメン）のアレとか色々．

帰ってからmatsuuさんのBarCamp-Tokyo2009用の下ごしらえっぽいモノとして，それっぽいgraphvizな絵をでっち上げた．
多分，もうちっと弄る．


上の絵をでっち上げていたら，#vhdlでhardware sound synthesize野郎が現れていた． :DDD

05/10 03:54:30 mad
    I'm planning on making sound generation stuff
05/10 03:56:23 mad
    most of that stuff is based around a phase register being incremented
    by the frequency on each sound cycle (which is pretty low rate -
    typically around 44khz)
05/10 04:02:43 bpadalino
    sounds like a cordic should help you out
05/10 04:04:46 hiyuh
    cordic is not for making sound, imho.
05/10 04:09:48 hiyuh
    that sounds like singletone, variable freq in narrow range, and
    presicion is not so important.
05/10 04:10:38 hiyuh
    maybe, making rom-based nco is enough to do.
05/10 04:14:39 bpadalino
    i don't know if a saw wave would sound very good, but as a phase
    accumulator - a cordic sounds like it would work well
05/10 04:30:24 hiyuh
    I meant cordic is expensive for that use.
05/10 04:30:29 hiyuh
    and saw wave + filter for singletone is not a possibility, anyway.
05/10 04:32:34 hiyuh
    phase accum -> sin or cos rom in appropriate precision -> singletone,
    it's simple rom-based nco.
05/10 04:40:47 bpadalino
    you really think a cordic is that expensive ?
05/10 04:51:49 hiyuh
    bpadalino: yes
05/10 04:51:58 bpadalino
    interesting
05/10 04:55:54 bpadalino
    hiyuh, so if you wanted to create 20 tones, how would you go about
    doing that ?
05/10 04:57:07 hiyuh
    20 tones in same time?
05/10 04:57:31 bpadalino
    yeah
05/10 04:59:05 hiyuh
    these tones are elaborate-time fixed or run-time fixed?
05/10 05:00:05 hiyuh
    I meant these tones are fixed before logic synthesize, or not.
05/10 05:00:29 bpadalino
    runtime fixed tones .. frequency fixed before synthesis, but phase
    programmable ..
05/10 05:00:44 bpadalino
    and i want the sum of the 20 tones on the output
05/10 05:07:54 hiyuh
    you mean "amplitude * (sin(2*pi*f1*t + theta1(t)) + ... sin(2*pi*f20*t
    + theta20(t)))"?
05/10 05:09:10 bpadalino
    yeah
05/10 05:10:53 hiyuh
    if I were you, I'd like to make semi-fixed digital filter or just
    do IFFT.
05/10 05:12:42 bpadalino
    that's what i had figured before, but i was just curious what someone
    else might have thought
05/10 05:13:00 hiyuh
    heh
05/10 05:14:18 bpadalino
    i would like to do my own generic systolic FFT sometime ... i think
    that might be fun
05/10 05:16:23 mad
    the tones parameters are written to at performance time
05/10 05:18:05 mad
    It's for music generation, so the applicable freqs are about 20hz to
    20khz (although tones over something like 4khz aren't particularly
    musical)
05/10 05:19:17 anonissimus
    mad: but as harmonics they are
05/10 05:19:33 mad
    Precision has to be at least 1%, esp. in the "most common range"
    (around 50hz ~ 1000hz)
05/10 05:19:50 mad
    anonissimus: yeah, but those are generated from another process
05/10 05:21:16 anonissimus
    ah
05/10 05:21:38 anonissimus
    know more on music than on generting it with hardware :)
05/10 05:21:57 mad
    My plan is: start with pure phase accumulator, then twist the phase
    around in a couple of functions (incl. one that uses multiplication),
    then use sine wave/funky waveform LUT, apply volume and panning,
    sum the channels together, DAC
05/10 05:24:12 mad
    Uses about 140 bits of registers per channel
05/10 05:27:44 mad
    A real practical design would actually be sample based instead
    (with samples in RAM)
05/10 05:29:23 hiyuh
    you know, your plan violates my assumption that described in the
    above expr.
05/10 05:29:25 hiyuh
    so what I was saying is not good way for you.
05/10 05:29:59 mad
    mm, right
05/10 05:31:35 mad
    sound synthesis isn't so hard because the sampling rate is low
    anyways... and you can do it well in software if you have enough CPU
05/10 05:32:14 hiyuh
    yeah, that's why soft synth is popular atm.
05/10 05:32:40 mad
    no kidding, since it pretty much solves it

つまり，敢えてsoftware sound synthesizeしないっつーことですか？
そいつは物好きだなぁ． :)

MeasureSLOC(&AL9); /* 2009/04 */

AでLで9なdiffstat，4月分．
[diffstat for AL9, for 2009/04.]

 a/bench/BENCH_NARROWER.vhd      |  148 -------
 a/vhdl/CPUMP.vhd                |  275 --------------
 a/vhdl/NARROWER.vhd             |  418 ----------------------
 a/vhdl/WIDER.vhd                |  350 ------------------
 b/bench/BENCH_HS_BUS.vhd        |  105 +++++
 b/bench/BENCH_SB.vhd            |  218 +++++++++++
 b/bench/BENCH_UDACCUM.vhd       |  100 +++++
 b/vhdl/HS_BUS.vhd               |  328 +++++++++++++++++
 b/vhdl/SB_MASTER.vhd            |  629 +++++++++++++++++++++++++++++++++
 b/vhdl/SB_SLAVE.vhd             |  339 ++++++++++++++++++
 b/vhdl/TX_SRC_MUX.vhd           |  180 +++++++++
 b/vhdl/TX_SX_FEBE.vhd           |  338 ++++++++++++++++++
 b/vhdl/UDACCUM.vhd              |  219 +++++++++++
 bench/BENCH_BCMUX.vhd           |    7 
 bench/BENCH_BER_IF_REG.vhd      |   92 ++--
 bench/BENCH_LDPCDDB.vhd         |  471 +++++++++++++++----------
 bench/BENCH_LDPCEDB.vhd         |  398 ++++++---------------
 bench/BENCH_PE2RST.vhd          |   49 +-
 bench/BENCH_TX_SMAP.vhd         |   43 +-
 bench/METABENCH_LDPCDDB.vhd     |  161 ++------
 bench/METABENCH_LDPCEDB.vhd     |  140 ++-----
 bench/METAMETABENCH_LDPCDDB.vhd |  104 +++++
 bench/METAMETABENCH_LDPCEDB.vhd |    4 
 stim/STIM_PN_DATA.vhd           |  156 +++++++-
 stim/STIM_RX_DATA_CARR.vhd      |  139 ++++++-
 stim/STIM_TX_DATA_CARR.vhd      |  135 ++++++-
 vhdl/AFIFO.vhd                  |   30 +
 vhdl/BER_IF_REG.vhd             |  743 ++++++++++++++++++++--------------------
 vhdl/CLDPCDOP.vhd               |   11 
 vhdl/COMMON_TYPE_PKG.vhd        |    7 
 vhdl/DFE_NEGOTIATE.vhd          |  282 ++++++++++-----
 vhdl/ELDPCDII.vhd               |   21 -
 vhdl/FCOD.vhd                   |   24 -
 vhdl/HD2BO.vhd                  |  123 +++---
 vhdl/LDPCD.vhd                  |   35 -
 vhdl/LDPCE.vhd                  |   41 +-
 vhdl/LDPCEDB.vhd                |   30 +
 vhdl/LLR2SC.vhd                 |   57 ++-
 vhdl/PE2RST.vhd                 |  310 +++++++++++-----
 vhdl/PN_BLOB.vhd                |   89 +---
 vhdl/PN_NEGOTIATE.vhd           |  274 ++++++++++----
 vhdl/PSQUASH.vhd                |   72 ++-
 vhdl/S2BER_IF.vhd               |   66 +--
 vhdl/SB2SSB.vhd                 |   83 +++-
 vhdl/SBSSBDD.vhd                |    8 
 vhdl/SFIFO.vhd                  |   16 
 vhdl/VTQUEUE.vhd                |    4 
 47 files changed, 4939 insertions(+), 2933 deletions(-)

やっぱ，10kSLOC逝ってないYO!!1 :DDD
[ZOMG, under 10kSLOC AGAIN!!1 :DDD]

VHDL -= function; VHDL -= procedure;

#vhdlにて，functionもprocedureもいらねぇだろうと寝言を言う野郎が出現．
[At #vhdl, t3h guy shoutz "no function and no procedure FTW!!1". So I'd have to say WTF.]

04/30 20:42:47 algoboy
    i need to create a load register, that load the value on a load
    signal, should the register be combinational or clocked? It has to
    hold the loaded values on the output until new values are loaded.
04/30 22:31:38 hw__
    I've been told that everywhere I call a function, the function is
    replaced by logic. So when I call 5 times a function I've 5 times
    the same logic in my FPGA. How about procedures? Does it depend on
    the class of formal/actual parameter?
04/30 23:51:23 algoboy
    hw__ : it depends on where you are calling the functions. If you
    write code that describes a circuit to do 5xtimes your function in
    one clock cycle then it will generate 5 times the hardware. But if
    you instead create a FSM and call the same function from 5 different
    states it should be synthesized to 1 function hardware, depending
    on if the synthesizing tool can schedule the operation and reuse
    the same hardware.
04/30 23:54:05 algoboy
    also the difference between a procedure and a function is that
    functions have a return value, procedures don't.
04/30 23:55:30 hw__
    algoboy: procedures can have "results" as well: If you use "inout"
    or "out" for parameter mode
04/30 23:57:38 algoboy
    yes, but i was just telling the difference between a procedure and
    function. a procedure doesn't return a value. The same as a void
    function in c/c++.
04/30 23:57:57 hiyuh
    no
04/30 23:58:47 algoboy
    no???
05/01 00:03:42 hiyuh
    procedure is procedure. function is function. not less, not more.
05/01 00:03:50 hiyuh
    if you really want to know what they are, read VHDL LRM or general
    CS book like MIT SICP.
05/01 00:08:56 algoboy
    yes a procedure is a procedure and a function is a function. I was
    just telling the difference between them. You can always transform
    a procedure to a function and a function to a procedure.
05/01 00:10:58 algoboy
    I don't see any benefit of using procedures and functions in VHDL. If
    you wan to create a "function" in VHDL create a circuit instead,
    sequential or combinational. This is a much better approach.
05/01 00:12:29 hiyuh
    whut?
05/01 00:13:14 hiyuh
    then, haven't you ever read the two-process method paper?
05/01 00:14:58 NULL[0]
    algoboy: are you a troll ?
05/01 00:15:47 hiyuh
    NULL[0]: i dont think so. :)
05/01 00:16:47 NULL[0]
    hiyuh: if you read his question, and the comments he made, I would
    not be surprised
05/01 00:17:16 longcat
    meh
05/01 00:18:28 algoboy
    hiyuh: Gaisler's two process method?? What does that have to do with
    procedures and functions.
05/01 00:19:00 hiyuh
    algoboy: yup.
05/01 00:19:33 algoboy
    yes i have, i uses the two process method almost all the time. But
    i never use functions and procedures. So i don't get your question.
05/01 00:20:49 hiyuh
    well, are you codin' vhdl as daily job, or?
05/01 00:21:18 algoboy
    no
05/01 00:21:53 algoboy
    i'm still a student
05/01 00:23:53 hiyuh
    okay, I got it, you should code more to realize why function/procedure
    are.
05/01 00:23:58 hiyuh
    I'm always codin' vhdl as daily job. no function/procedure is
    nightmare for me.
05/01 00:26:15 algoboy
    The only benefit i could think of is if you create your own library
    so that you can reuse.
05/01 00:31:21 hiyuh
    what you're saying looks like "always code by using machine language
    in HEX editor" to me.
05/01 00:31:27 hiyuh
    or, sounds like "paste same code from existing ones, b/c I don't
    like any abstraction."
05/01 00:33:04 drichards
    isn't abstraction the whole point of an HDL?
05/01 00:33:37 MatthiasM
    I use functions for simple things - like counting leading zeros etc
05/01 00:34:06 algoboy
    VHDL is not a programming language so i wouldn't write any machine
    code. I use VHDL to describe hardware and and prefer to work on the
    RTL level.
05/01 00:34:27 MatthiasM
    or procedures for updating more complex counters like this: lsb <=
    (lsb + inc) mod X; msb <= msb + (lsb + inc) / X;
05/01 00:35:06 *
    hiyuh lolz @ "VHDL is not a programming language"
05/01 00:35:15 MatthiasM
    functions are much more flexible as you can decide where to store
    the return value when you call it (or use it directly in an IF)
05/01 00:35:51 algoboy
    hiyuh: :/
05/01 00:35:59 MatthiasM
    procedures can have more then one return value - but you must decide
    if the values are passed/returned as signal or variable
05/01 00:36:43 MatthiasM
    all functions and procedures are basicly combinatorical logic -
    if you need something with a clock - write a new entity
05/01 00:37:22 algoboy
    MatthiasM: so why not write combinatorial logic all the time?
05/01 00:37:35 MatthiasM
    algoboy: LOL
05/01 00:37:50 algoboy
    MatthiasM: instead of a function or procedure
05/01 00:38:29 MatthiasM
    the example of the procedure above - is about ~10 lines of code -
    I need it in 4 places - calling it takes 1 line of code
05/01 00:38:45 MatthiasM
    and it even works when the bit width of the busses are different
    for each call
05/01 00:39:42 drichards
    which is why I like subprogs
05/01 00:39:55 algoboy
    MatthiasM: create the same procedure as a circuit. Use generate to
    generate x instances and also use genric.
05/01 00:39:55 drichards
    they can react to the act bus width, register width, etc.
05/01 00:39:58 algoboy
    the same thing
05/01 00:40:57 MatthiasM
    algoboy: I can call a function/procedure inside a clocked process
    and inside nested control edges - this makes it very easy to write
    complex logic with sequential source code
05/01 00:41:34 MatthiasM
    as a designer I want to write code that is A) easy to write B)
    easy to read C) easy to change
05/01 00:41:56 MatthiasM
    and it's the tools job to create an efficient logic implementation
    based on my source code
05/01 00:43:10 MatthiasM
    ofcourse you have to be careful to not create to wide logic functions
    - which can easily happen if you nest IFs - or check the result of
    combinatorical functions (like "IF x+1 == y THEN .... END IF;")
05/01 00:43:43 MatthiasM
    algoboy: if you understand these - then you can create a complex
    design in a short time
05/01 00:43:51 algoboy
    MatthiasM: i prefere to write synthesizable code, targeting low power,
    low area. Using higher abstraction you rely much on the synthesizing
    tool to do the job for you.
05/01 00:44:10 NULL[0]
    ...
05/01 00:44:32 MatthiasM
    yep - that's why I use Quartus - it's synthesizer is very good -
    it's very hard to create more efficient logic by hand
05/01 00:45:54 algoboy
    oh, fpga synthesizing is one thing, but i am running asic flow and
    it is a huge difference.
05/01 00:46:19 tzanger
    MatthiasM: quartus is for atmel, right?
05/01 00:46:27 MatthiasM
    Altera
05/01 00:46:30 algoboy
    yes
05/01 00:46:35 algoboy
    altera
05/01 00:47:32 tzanger
    er altera
05/01 00:47:33 tzanger
    duh
05/01 00:47:41 tzanger
    I knew it was an A. :-)
05/01 00:47:47 algoboy
    :p
05/01 00:47:49 *
    hiyuh petz NULL[0]. :)
05/01 00:48:09 MatthiasM
    algoboy: take a look at some old code: http://pastebin.com/d418ebc0e
05/01 00:49:10 MatthiasM
    the production code uses constants instead of hard coded values
    ofcourse
05/01 00:52:14 algoboy
    MatthiasM: VGA controller?
05/01 00:52:25 MatthiasM
    sync generator for DVI
05/01 00:52:34 MatthiasM
    (VGA doesn't use DE signal)
05/01 00:52:52 algoboy
    oh :)
05/01 00:53:17 MatthiasM
    but it started as VGA generator - that's why the clock is called
    vga_clk
05/01 00:53:41 hiyuh
    rename FTW!!1 :)
05/01 00:54:15 MatthiasM
    algoboy: see the splitted counter in line 28 and the compare in line
    35 ? the current code uses procedures for increment and a function
    for compare
05/01 00:54:20 algoboy
    MatthiasM: that is nice code :) no functions or procedures :)
05/01 00:54:45 MatthiasM
    that way I can just write "IF compare(row_cnt2, row_cnt1, 12, 805)
    then .... end if;"
05/01 00:56:28 MatthiasM
    algoboy: eg http://pastebin.com/d7c8c5b34
05/01 00:56:41 MatthiasM
    much more readable
05/01 00:57:52 algoboy
    yes it is, if you know what the functions does.
05/01 00:58:18 MatthiasM
    that's why you can put comments into the VHDL files
05/01 01:00:08 algoboy
    :p
05/01 01:00:24 *
    hiyuh sticks more popcorn to the microwave.
05/01 01:00:40 *
    MatthiasM steals hiyuh's popcorn
05/01 01:01:00 hiyuh
    lol
05/01 01:01:16 MatthiasM
    :DD

ポップコーンを喰えたので良しとする． :DDD
[PLESIOUS POPCORN TIME, YUM!!1 :DDD]