m0ronic coder in LOL way: VHDL -= function; VHDL -= procedure;

#vhdlにて，functionもprocedureもいらねぇだろうと寝言を言う野郎が出現．
[At #vhdl, t3h guy shoutz "no function and no procedure FTW!!1". So I'd have to say WTF.]
04/30 20:42:47 algoboy
    i need to create a load register, that load the value on a load
    signal, should the register be combinational or clocked? It has to
    hold the loaded values on the output until new values are loaded.
04/30 22:31:38 hw__
    I've been told that everywhere I call a function, the function is
    replaced by logic. So when I call 5 times a function I've 5 times
    the same logic in my FPGA. How about procedures? Does it depend on
    the class of formal/actual parameter?
04/30 23:51:23 algoboy
    hw__ : it depends on where you are calling the functions. If you
    write code that describes a circuit to do 5xtimes your function in
    one clock cycle then it will generate 5 times the hardware. But if
    you instead create a FSM and call the same function from 5 different
    states it should be synthesized to 1 function hardware, depending
    on if the synthesizing tool can schedule the operation and reuse
    the same hardware.
04/30 23:54:05 algoboy
    also the difference between a procedure and a function is that
    functions have a return value, procedures don't.
04/30 23:55:30 hw__
    algoboy: procedures can have "results" as well: If you use "inout"
    or "out" for parameter mode
04/30 23:57:38 algoboy
    yes, but i was just telling the difference between a procedure and
    function. a procedure doesn't return a value. The same as a void
    function in c/c++.
04/30 23:57:57 hiyuh
    no
04/30 23:58:47 algoboy
    no???
05/01 00:03:42 hiyuh
    procedure is procedure. function is function. not less, not more.
05/01 00:03:50 hiyuh
    if you really want to know what they are, read VHDL LRM or general
    CS book like MIT SICP.
05/01 00:08:56 algoboy
    yes a procedure is a procedure and a function is a function. I was
    just telling the difference between them. You can always transform
    a procedure to a function and a function to a procedure.
05/01 00:10:58 algoboy
    I don't see any benefit of using procedures and functions in VHDL. If
    you wan to create a "function" in VHDL create a circuit instead,
    sequential or combinational. This is a much better approach.
05/01 00:12:29 hiyuh
    whut?
05/01 00:13:14 hiyuh
    then, haven't you ever read the two-process method paper?
05/01 00:14:58 NULL[0]
    algoboy: are you a troll ?
05/01 00:15:47 hiyuh
    NULL[0]: i dont think so. :)
05/01 00:16:47 NULL[0]
    hiyuh: if you read his question, and the comments he made, I would
    not be surprised
05/01 00:17:16 longcat
    meh
05/01 00:18:28 algoboy
    hiyuh: Gaisler's two process method?? What does that have to do with
    procedures and functions.
05/01 00:19:00 hiyuh
    algoboy: yup.
05/01 00:19:33 algoboy
    yes i have, i uses the two process method almost all the time. But
    i never use functions and procedures. So i don't get your question.
05/01 00:20:49 hiyuh
    well, are you codin' vhdl as daily job, or?
05/01 00:21:18 algoboy
    no
05/01 00:21:53 algoboy
    i'm still a student
05/01 00:23:53 hiyuh
    okay, I got it, you should code more to realize why function/procedure
    are.
05/01 00:23:58 hiyuh
    I'm always codin' vhdl as daily job. no function/procedure is
    nightmare for me.
05/01 00:26:15 algoboy
    The only benefit i could think of is if you create your own library
    so that you can reuse.
05/01 00:31:21 hiyuh
    what you're saying looks like "always code by using machine language
    in HEX editor" to me.
05/01 00:31:27 hiyuh
    or, sounds like "paste same code from existing ones, b/c I don't
    like any abstraction."
05/01 00:33:04 drichards
    isn't abstraction the whole point of an HDL?
05/01 00:33:37 MatthiasM
    I use functions for simple things - like counting leading zeros etc
05/01 00:34:06 algoboy
    VHDL is not a programming language so i wouldn't write any machine
    code. I use VHDL to describe hardware and and prefer to work on the
    RTL level.
05/01 00:34:27 MatthiasM
    or procedures for updating more complex counters like this: lsb <=
    (lsb + inc) mod X; msb <= msb + (lsb + inc) / X;
05/01 00:35:06 *
    hiyuh lolz @ "VHDL is not a programming language"
05/01 00:35:15 MatthiasM
    functions are much more flexible as you can decide where to store
    the return value when you call it (or use it directly in an IF)
05/01 00:35:51 algoboy
    hiyuh: :/
05/01 00:35:59 MatthiasM
    procedures can have more then one return value - but you must decide
    if the values are passed/returned as signal or variable
05/01 00:36:43 MatthiasM
    all functions and procedures are basicly combinatorical logic -
    if you need something with a clock - write a new entity
05/01 00:37:22 algoboy
    MatthiasM: so why not write combinatorial logic all the time?
05/01 00:37:35 MatthiasM
    algoboy: LOL
05/01 00:37:50 algoboy
    MatthiasM: instead of a function or procedure
05/01 00:38:29 MatthiasM
    the example of the procedure above - is about ~10 lines of code -
    I need it in 4 places - calling it takes 1 line of code
05/01 00:38:45 MatthiasM
    and it even works when the bit width of the busses are different
    for each call
05/01 00:39:42 drichards
    which is why I like subprogs
05/01 00:39:55 algoboy
    MatthiasM: create the same procedure as a circuit. Use generate to
    generate x instances and also use genric.
05/01 00:39:55 drichards
    they can react to the act bus width, register width, etc.
05/01 00:39:58 algoboy
    the same thing
05/01 00:40:57 MatthiasM
    algoboy: I can call a function/procedure inside a clocked process
    and inside nested control edges - this makes it very easy to write
    complex logic with sequential source code
05/01 00:41:34 MatthiasM
    as a designer I want to write code that is A) easy to write B)
    easy to read C) easy to change
05/01 00:41:56 MatthiasM
    and it's the tools job to create an efficient logic implementation
    based on my source code
05/01 00:43:10 MatthiasM
    ofcourse you have to be careful to not create to wide logic functions
    - which can easily happen if you nest IFs - or check the result of
    combinatorical functions (like "IF x+1 == y THEN .... END IF;")
05/01 00:43:43 MatthiasM
    algoboy: if you understand these - then you can create a complex
    design in a short time
05/01 00:43:51 algoboy
    MatthiasM: i prefere to write synthesizable code, targeting low power,
    low area. Using higher abstraction you rely much on the synthesizing
    tool to do the job for you.
05/01 00:44:10 NULL[0]
    ...
05/01 00:44:32 MatthiasM
    yep - that's why I use Quartus - it's synthesizer is very good -
    it's very hard to create more efficient logic by hand
05/01 00:45:54 algoboy
    oh, fpga synthesizing is one thing, but i am running asic flow and
    it is a huge difference.
05/01 00:46:19 tzanger
    MatthiasM: quartus is for atmel, right?
05/01 00:46:27 MatthiasM
    Altera
05/01 00:46:30 algoboy
    yes
05/01 00:46:35 algoboy
    altera
05/01 00:47:32 tzanger
    er altera
05/01 00:47:33 tzanger
    duh
05/01 00:47:41 tzanger
    I knew it was an A. :-)
05/01 00:47:47 algoboy
    :p
05/01 00:47:49 *
    hiyuh petz NULL[0]. :)
05/01 00:48:09 MatthiasM
    algoboy: take a look at some old code: http://pastebin.com/d418ebc0e
05/01 00:49:10 MatthiasM
    the production code uses constants instead of hard coded values
    ofcourse
05/01 00:52:14 algoboy
    MatthiasM: VGA controller?
05/01 00:52:25 MatthiasM
    sync generator for DVI
05/01 00:52:34 MatthiasM
    (VGA doesn't use DE signal)
05/01 00:52:52 algoboy
    oh :)
05/01 00:53:17 MatthiasM
    but it started as VGA generator - that's why the clock is called
    vga_clk
05/01 00:53:41 hiyuh
    rename FTW!!1 :)
05/01 00:54:15 MatthiasM
    algoboy: see the splitted counter in line 28 and the compare in line
    35 ? the current code uses procedures for increment and a function
    for compare
05/01 00:54:20 algoboy
    MatthiasM: that is nice code :) no functions or procedures :)
05/01 00:54:45 MatthiasM
    that way I can just write "IF compare(row_cnt2, row_cnt1, 12, 805)
    then .... end if;"
05/01 00:56:28 MatthiasM
    algoboy: eg http://pastebin.com/d7c8c5b34
05/01 00:56:41 MatthiasM
    much more readable
05/01 00:57:52 algoboy
    yes it is, if you know what the functions does.
05/01 00:58:18 MatthiasM
    that's why you can put comments into the VHDL files
05/01 01:00:08 algoboy
    :p
05/01 01:00:24 *
    hiyuh sticks more popcorn to the microwave.
05/01 01:00:40 *
    MatthiasM steals hiyuh's popcorn
05/01 01:01:00 hiyuh
    lol
05/01 01:01:16 MatthiasM
    :DD