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2006/06/08

gated clock, register RAM

修行の成果(?)として,BK in VHDLでもやってみる.
[Here is my BK in VHDL.]

以下のプロセスpFOOとpBARは根本的に別モノである.
[The process of pFOO and pBAR are totally different.]

pFOO : process (ixRST, iCLK)
begin
if (ixRST = '0') then
-- RESET IT!
:
:
elsif (iCLK'event and iCLK = '1') then
if (ixEN = '0') then
-- DO IT!
:
:
end if;
end if;
end process;
----------------------------------------------
pBAR : process (ixRST, iCLK)
begin
if (ixRST = '0') then
-- RESET IT!
:
:
elsif (iCLK'event and iCLK = '1' and ixEN = '0') then
-- DO IT!
:
:
end if;
end process;

以下の記述の違いで,
インプリするデバイスによってはハマる可能性がある.
[You may choke by difference of between FOO and BAR
when it was implement into specific HW.]

archtecture RTL of FOO is
subtype tADDR is std_logic_vector(AL-1 downto 0);
subtype tWORD is std_logic_vector(WL-1 downto 0);
:
:
type tMEMORY is array(0 to 2**AL-1) of tWARD;
:
:
signal rRA : tADDR;
signal rINIT_RD : std_logic;
signal aRAM : tMEMORY;
begin
pRAM_RD : process (iCLK)
begin
if (iCLK'event and iCLK = '1') then
rINIT_RD <= iINIT_RD;
rRA <= iRA;
if (rINIT_RD = '1') then
oDOUT_RD <= (others => '0');
else
oDOUT_RD <= aRAM(conv_integer(rRA));
end if;
end if;
end process;
:
:
pRAM_WR : process (iCLK)
begin
if (iCLK'event and iCLK = '1') then
if (iWE = '1') then
aRAM(conv_integer(iWA)) <= iDIN_WR;
end if;
end if;
end process;
end RTL;
----------------------------------------------
archtecture RTL of BAR is
subtype tADDR is std_logic_vector(AL-1 downto 0);
subtype tWORD is std_logic_vector(WL-1 downto 0);
:
:
type tMEMORY is array(0 to 2**AL-1) of tWARD;
:
:
signal aRAM : tMEMORY;
begin
pRAM_RD : process (iCLK)
begin
if (iCLK'event and iCLK = '1') then
if (iINIT_RD = '1') then
oDOUT_RD <= (others => '0');
else
oDOUT_RD <= aRAM(conv_integer(iRA));
end if;
end if;
end process;
:
:
pRAM_WR : process (iCLK)
begin
if (iCLK'event and iCLK = '1') then
if (iWE = '1') then
aRAM(conv_integer(iWA)) <= iDIN_WR;
end if;
end if;
end process;
end RTL;

違いの分かる漢のVHDL,か? :P
[Hey, any of you guy of VHDL got it? :P]

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