[At #vhdl@freenode.net.]
06/23 00:02:31 Manny
06/23 00:02:42 Manny
can I declare entity foo in file bar.vhd?
06/23 00:03:21 hiyuh
06/23 00:03:35 Manny
I have a working architecture for an un-delayed 4:1 multiplexer, and
I want to convert it to a delayed 4:1-multiplexer (wrt data lines),
but undelayed (wrt address line), which I want to implement by a
staged layout like:
06/23 00:04:20 Manny
architecture arch1 of mux is ... end arch1; arch2 of mux is ... 4
delay stages, MUX1: mux port map (output of delay, ...); end arch2;
06/23 00:04:49 Manny
I wonder whether it is possible to configure the mux used inside
the mux arch2 to use the mux arch1
06/23 00:08:00 Manny
ok, I figured how how the lattter should work
06/23 00:09:27 Manny
hiyuh: maybe I could show you some code - maybe in private?
06/23 00:10:08 Manny
it's really short and simple :)
06/23 00:11:39 hiyuh
hmm, you mean pm? why?
06/23 00:13:12 Manny
06/23 00:14:17 Manny
hiyuh: my VHDL compiler bails (I'm absolving an online remote hands-on
course at university)
06/23 00:15:34 Manny
hiyuh: here is the compiler output:
06/23 00:15:58 Manny
it even tells me that it does not know about std_logic_vector -
this is odd...
06/23 00:18:13 `fred`
no it is not
06/23 00:19:46 Manny
`fred`: what am I doing wrong besides a few syntax errors I just
06/23 00:20:51 `fred`
you have to repeat the use statements for each entity
06/23 00:21:27 Manny
`fred`: thanks a million! :)
06/23 00:22:22 `fred`
second point: learn how to use (others => '...') instead of writing
06/23 00:30:48 Manny
`fred`: maybe you could give me a URL, or a quick example? I'd
really like to learn this :) I just peeked at the VHDL cookbook,
and it seems to use a few constructs but I don't grasp them.
06/23 00:31:49 `fred`
when others => Y <= "XXXXXXXXXXXXXXXX"; <=> when others => Y <=
(others => 'X);
06/23 00:32:10 `fred`
except that it is independent from the size of the vector
06/23 00:34:00 Manny
maybe I lack some decent portion of knowledge of VHDL internals. "when
others => Y <= (others => 'X);" seems to give me a syntax error
06/23 00:34:20 `fred`
one ' is missing
06/23 00:34:23 `fred`
06/23 00:34:47 hiyuh
06/23 00:34:50 Manny
so 'X' is "expanded" to fit the LHS. neat.
06/23 00:35:44 Manny
hiyuh: thanks for your comments! Actually, I figured out all of
these myself :))
06/23 00:35:54 hiyuh
06/23 00:36:00 `fred`
Manny: the full notation is e.g. ( 0 => '0', 1 => '1', others =>
'Z'), it should be describe in the aggregate chapter of your book
06/23 00:37:02 Manny
however, using arch1 inside arch2 still does not seem to work. It
seems to nest arch2 mux components inside my arch2 component, which
is of course not useful (infinite recursion)
06/23 00:37:21 Manny
let me show you my testbench, maybe the configuration statements
are conflicting
06/23 00:39:04 Manny
that's my test bench: http://rifers.org/paste/vhdlforyou/show/7549
06/23 00:42:10 Manny
also let me re-paste the mux file:
06/23 00:42:46 Manny
06/23 00:43:37 hiyuh
06/23 00:44:49 hiyuh
why on the earch should we comment 'in' and 'out' even if there is
syntactic 'in' and 'out'?
06/23 00:45:01 *
hiyuh zomgs
06/23 00:48:04 Manny
hiyuh: I do not like the in/out syntax of VHDL with respect to
that. The in/out looks rather "buried" inside the syntactical
structure if you specify an array of parameters
06/23 00:49:05 Manny
as an electrical engineerer, in/out is the MAIN aspect of a system :D
06/23 00:49:09 Manny
at least of a concentrated system
06/23 00:51:21 hiyuh
array of parameters? wth is it?
06/23 00:51:24 hiyuh
`fred`: btw, I found really buggy optimize option in ISE 9.2i/10.1
which breaks many core generator's craps. are you survivin' w/ v5? :p
06/23 00:52:12 `fred`
hiyuh: I've got the strangest bug with 10.1, it was optimising away
most of my microblaze without any reason
06/23 00:53:24 hiyuh
yup, you enabled Global Optimization at Map?
06/23 00:53:29 hiyuh
I'm really sure it will do byggy optimization.
06/23 00:53:43 Manny
hiyuh: you may also call it tuple. You know, A, B, C, D: in type ...;
06/23 00:54:14 Manny
hiyuh: however, I still do not understand what I am doing wrong
06/23 00:54:17 `fred`
hiyuh: only when the design was no longer fitting, and in this case
it was not helping :/
06/23 00:56:13 hiyuh
Manny: I'm saying about comment manner, not vhdl specific. and it's
unrelated point about what you're stucking.
06/23 00:58:42 Manny
maybe the "for mux2: mux use entity work.mux(arch2); end for;"
statement affects all mux building blocks, and not just the outer one?
06/23 01:00:03 hiyuh
`fred`: I was investigating ISE's buggy optimization like many trying
default w/ 1 option chnaging. at least, Global Optimization at Map
will break post-PAR model, I figured out.
06/23 01:01:31 hiyuh
and Optimize Instantiated Primitives at Synthesize will optimize
away some top entity's port. it vomits error at Translate.
06/23 01:03:00 hiyuh
Manny: if you're not sure what/how configuration works, don't use it.
06/23 01:03:57 hiyuh
just analyze and elaborate 1-to-1 entity-architecture.
06/23 01:04:06 `fred`
hiyuh: even with sp1 installed ?
06/23 01:04:20 hiyuh
you mean 10.1 sp1?
06/23 01:04:22 Manny
hiyuh: so I am mis-using the configuration?
06/23 01:04:25 `fred`
06/23 01:04:47 Manny
hiyuh: I can of course read into it, if you tell me that what I am
trying to do is definitly possible with the basic approach :)
06/23 01:05:11 hiyuh
`fred`: release 10.1.01 (10.1 + sp1, IIRC) is still buggy. :P
06/23 01:06:08 Manny
again, the idea is: Use mux with architecture arch2. Inside this mux,
use another mux with architecture arch1. Naively concluding from what
I have seen, I AM actually using a 1:1 entity-architecture mapping.
06/23 01:06:16 `fred`
hiyuh: well, I'm anyway not really surprised
06/23 01:06:40 hiyuh
yup, we know ISE is always buggy. :p
06/23 01:07:43 hiyuh
Manny: 1-to-1 entity-architecture doesn't need any explicit
06/23 01:07:58 Manny
hiyuh: you mean like "each entity just has one architecture"?
06/23 01:09:12 Manny
hiyuh: the thing is, for non-nested layouts all my configurations
work fine. Now, I am trying to nest an entity of one architecture
into another architecture of the same entity, and the compiler bails.
06/23 01:09:35 hiyuh
Manny: yup, until you realized configuration magic.
06/23 01:10:52 Manny
hiyuh: I am also not sure whether I am seeing a compiler issue, or
whether my configurations are wrong. If you can confirm me latter
[maybe even giving hints about the right configuration], I will
continue the approach :)
06/23 01:11:33 hiyuh
if you use sane vhdl simulator/synthesizer, valid configuration does
work even if design has nested entity.
06/23 01:12:53 Manny
ok, thanks for all your efforts. It's great to have such a kind and
quick support for VHDL :)

何時もムカつく事だけど、buggyなbin blobはどうにかならんかね。「releaseダルい」の件では、少し壊れている方が可愛げがあるって言ったけど、それは自分で直せる可能性とか遊びドコロがあるからって意味であって、ぶっ壊れているから面白いって意味じゃない。オープンソースキチガイってわけじゃないけど、仕事で作ってるならもう少しテストしてからリリースしたらどうなんだ?もう手前でwork around探すのは疲れたよ、パトラッシュ。 :P
[Everytime buggy bin blob piss me off. I said "I kinda prefer to play recent one w/ itty-bitty bugz" though, I meant it has a part of what I can play w/ it in the source code, not unfixable buggy behavior. So, I'm not open source nazi. You, who earns from your code, should be responsible w/ it. I'm really tired to find t3h work around for myself. :P]

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