bus(eBIDIRECT).collison.karma--;

#vhdl@irc.freenode.netで双方向バスの話．
[Here is snippet log of #vhdl@irc.freenode.net.
The subject is bidirectional bus.]

10/13 23:48:13 joe2371
    I do not understand iobuf.  What happens if I is driven to (NOT IO)?
    Which input wins?
10/13 23:50:28 joe2371
    Would this condition tie Vcc to ground?
10/13 23:57:15 joe2371
    Do I use T to select input vs. output mode?  The table I have in my
    documentation does not make this clear to me.
10/14 00:08:35 joe2371
    I am going to assume that the table is simply unclear and the
    schematic symbol probably represents a combination of obuft with
    ibuf.  That would make a lot of sense, but I am surprised that the
    Xilinx documentation would describe the operation the way it does.
    Unless my original interpretation of the documentation is correct and
    I need to use seperate ibuf and obuft components in my design.  Ugh.
10/14 00:23:54 joe2371
    Please look at this and tell me if I am right or wrong. Thank
    you. http://rafb.net/p/y1DT3Y68.html
10/14 00:30:40 joe2371
    Hans, can you please answer my question if you have time?
    http://rafb.net/p/y1DT3Y68.html
(BEGIN_SNIPPET_FROM_THE_LINK)
iobuf
 
 T ____
       |
     |\|
 I __| \______ IO
     | /   |
     |/    |
       /|  |
 O ___/ |__|
      \ |
       \|
 
 
Xilinx iobuf table:
 
T I IO O
1 X Z X
0 1 1 1
0 0 0 0
 
But I think I want this:
 
T I IO O
1 X 0 0
1 X 1 1
0 0 0 X
0 1 1 X
 
Is this what I get?
(END_SNIPPET_FROM_THE_LINK)
10/14 00:31:57 joe2371
    I am trying to learn how to use the iobuf component and the
    documentation is not clear to me.
10/14 00:33:12 joe2371
    And I don't know how to test my understanding in simulation because
    it is a buffer.
10/14 01:31:34 hiyuh
    joe2371: did you understand...
10/14 01:31:46 hiyuh
    1. "I is input from inside of FPGA, to output to IO"?
10/14 01:31:53 hiyuh
    2. "O is output from outside of FPGA, to input from IO"?
10/14 01:31:55 hiyuh
    3. "buffered I and unbuffered O is shared at inside of FPGA"?
10/14 01:32:33 joe2371
    IO is pin side. I,O are FPGA side, right?
10/14 01:32:47 hiyuh
    yup
10/14 01:33:23 joe2371
    does T select input/output mode?  I mean, what happens if I is 0
    but IO goes to 1?
10/14 01:35:19 joe2371
    I mean, if SRAM is driving IO, how do I disable I from trying to
    drive it also?
10/14 01:36:08 joe2371
    Do I have to output Z to the I?
10/14 01:37:07 hiyuh
    nope, T selects buffered I's state (it may not be IO's state) to 'Z'
    (T = 1) or unbuffered I (T = 0).
10/14 01:38:13 joe2371
    So T disables the I pin of the iobuf, but does prevent IO from
    changing O?
10/14 01:40:12 joe2371
    I am trying to learn how to read the value of IO into the FPGA.
10/14 01:42:06 joe2371
    I guess I still don't understand. And I have not been able to simulate
    an iobuf to learn how it works. :-/
10/14 01:44:20 joe2371
    Maybe you have answered my question already.  If T=1 makes I=Z,
    then hopefully O=IO.
10/14 01:45:46 joe2371
    I am sorry if I do not immediately understand your explanation.
10/14 01:52:39 hiyuh
    "if T <= 1, then buffered I <= 'Z' and O <= IO", "if T =
    0, buffered I <= I. so O and IO <= wired(buffered I, IO comes
    from as others' output)"
10/14 01:53:44 joe2371
    Thank you.  I think that is exactly what I want.
10/14 01:53:55 hiyuh
    yw
10/14 01:57:27 hiyuh
    ... so bus collision make your day, I guess. :p
10/14 01:57:35 hiyuh
    s/make/makes/
10/14 01:57:36 *
    hiyuh runs.
10/14 01:59:37 hiyuh
    FYI, to read about "I-BEFORE" and "OUT-AFTER" for ucf files' timing
    constrain would be useful.
10/14 01:59:53 hiyuh
    s/I-/IN-/
10/14 02:00:31 joe2371
    oh, no.  This means "O and IO <= wired(I, IO comes from SRAM)"
    means two inputs on same bus.  That is not what I want, of course.
10/14 02:01:34 hiyuh
    yeah
10/14 02:02:13 joe2371
    "assign IO = I and assign IO = SRAM-output" at the same time is not
    what I want.  Does this mean I cannot use iobuf for my design?
10/14 02:03:05 joe2371
    I will look for "I-BEFORE" and "OUT-AFTER" for ucf files.
10/14 02:07:54 hiyuh
    so, to keep IO <= 'Z' w/ T = '1' as neutral. when you really want
    to output via IOBUF, make sure SRAM is input-state before output
    via IOBUF. when others, you should think SRAM may be output-state.
10/14 02:08:53 joe2371
    oh, I see.
10/14 02:08:56 hiyuh
    otherwise, bus collisoin makes your day. :p

snipLog("/me@#vhdl");

久しぶりにIRCのログを貼り付けてみる．
#vhdl@irc.freenode.netでMemory I/Fなお話．
[Here is a snippet log #vhdl@irc.freenode.net. The subject is a memory I/F.]

10/13 04:14:34 joe2371
    Are questions about schematics portable between languages and
    software?  I'm trying to find out the correct way to connect one
    signal to two FPGA pins.  Do I want to treat my signal as a 1-bit bus
    and put two taps on it?  I thought that bus taps required the nets
    on both sides to have compatible names (eg: Addr(19:0) -> Addr(15)
    and not Addr(19:0) -> Foo).  Is this splitting best done in the pin
    assignment file (.ucf) ?
10/13 04:28:44 hiyuh
    depends on transfer speed, imho.
10/13 04:32:33 hiyuh
    e.g. I'm now working 8 boards (each one has 4 virtex4).
10/13 04:33:21 hiyuh
    each virtex4 will input/output from/to others, the data syncs 128MHz
    via simple parallel bus.
10/13 04:33:26 hiyuh
    the output to outside of the board will be syncs 256MHz as LVDS.
10/13 04:33:38 hiyuh
    sample pic is http://dev.gentoo.gr.jp/~hiyuh/misc/V4LXB.jpg
10/13 04:35:12 hiyuh
    reference clock's accuracy and deskewing of sync clock is also PITA.
10/13 04:35:32 hiyuh
    s/is/are/
10/13 04:38:47 joe2371
    That's a nice looking board.  The Virtices have fans on them?
10/13 04:39:58 hiyuh
    yup
10/13 04:41:38 hiyuh
    the left side one is japanese tobacco box, btw.
10/13 04:41:59 joe2371
    With the letter C ?
10/13 04:42:10 hiyuh
    yeah
10/13 04:43:12 joe2371
    pretty neat.  I'd hate to think what it costs.
10/13 04:44:27 joe2371
    Do tools exists that can map a design across multiple chips
    automatically?
10/13 04:45:51 joe2371
    ...basically treating four FPGAs like one larger one, I mean.
    The more I think about it, the less likely I imagine that is.
10/13 04:46:02 hiyuh
    my bosses said, one Virtex4 LX200 (the best one of Virtex4 LX series)
    will costs about 1000000 yen. but it should depends on quantities
    of order, I guess. :p
10/13 04:47:05 joe2371
    It's something like 1000 yen to the dollar, I think.  Ouch.
10/13 04:47:43 hiyuh
    I dunno that neat tool which automatically map it to them.
10/13 04:48:29 joe2371
    I guess if they are Virtex chips, you are stuck with Xilinx tools.
10/13 04:49:39 hiyuh
    yeah, it's kinda corporate (or project's?) policy, maybe.
10/13 04:50:48 hiyuh
    so I can take a screenshot of fsckin' ISE crashing per working day. :p
10/13 04:51:15 joe2371
    Only once per day?  ISE crashes sometimes 3-5 times on me.
10/13 04:51:50 joe2371
    At least it recovers my work OK. (so far)
10/13 04:52:49 hiyuh
    I'd have to treat that crap *gently*, b/c it's my job atm. :p
10/13 04:55:31 hiyuh
    well, using same name in sch and logical vhdl design is a bit of
    difficult, if it's a dead-lined project.
10/13 04:57:03 hiyuh
    and ucf craps are not only for constraining the pin assign.
10/13 04:57:40 hiyuh
    splitting them to ucf is a good way to go, though.
10/13 04:57:44 joe2371
    Ok. My lab homework assignment is to create a 1MB memory controller
    with only 14 address pins.  I am trying to connect one signal to
    two memory chips (same signal, different pins).
10/13 04:58:04 hiyuh
    heh
10/13 04:58:09 joe2371
    I created that 1-bit bus with two taps.
10/13 04:58:16 joe2371
    I don't know if it works, though.
10/13 05:00:58 hiyuh
    have you consider about the memories' I/F, driving load, or something?
10/13 05:01:19 hiyuh
    s/consider/considered/
10/13 05:02:16 joe2371
    oh, no.  I am still experimenting with my initial concept for
    the design.  I don't know what difficulties to expect.
10/13 05:03:31 hiyuh
    ah, ok. then first step is to gaze the memories' spec sheet, I
    guess. :)
10/13 05:03:49 joe2371
    The documentation for the board did not talk about driving load
    that I can remember.  It just says which pins of the FPGA are tied
    to which pins of the SRAMs
10/13 05:04:04 joe2371
    I have the specs for the SRAM here
10/13 05:05:17 hiyuh
    SRAM? then it doesn't need to be refreshing, right?
10/13 05:05:25 joe2371
    right
10/13 05:05:39 joe2371
    yes, I am lucky it is SRAM
10/13 05:06:18 joe2371
    But I am unlucky I have only 14 address bus pins connected.
10/13 05:07:50 hiyuh
    SRAM's address is 14bits?
10/13 05:08:02 hiyuh
    or you have only 14bits on FPGA to specify SRAM's address but SRAM's
    address is not 14bits?
10/13 05:09:38 joe2371
    no, 18 bits for a 16-bit memory location, plus upper byte and lower
    byte pins, plus there are two chips.  So SRAMs actually have 20-bit
    address (of bytes).  But I have a CPU which has only 14 address pins
    connected to the FPGA.
10/13 05:10:12 joe2371
    I want to use the LSB of the address to select upper/lower byte.
    And LSB+1 to select SRAM0/SRAM1.
10/13 05:10:34 joe2371
    the missing MSBits are provided from a register tied to a port.
10/13 05:11:16 joe2371
    but I need to connect the LSB and LSB+1 to four pins.
10/13 05:11:28 hiyuh
    oic
10/13 05:14:44 joe2371
    I just thought of something.  If chip enable is off, these SRAMs
    go to low power mode.  Maybe I should organize my pins differently
    so that I will use less power when the memory is less than half
    full... Hmmm... I'll think about that.
10/13 05:16:22 joe2371
    I think it means changing one line of HDL.  Then I can say my design
    not only works, but is also efficient. :-)
10/13 05:17:43 joe2371
    Nevermind.  CE only goes high on reads and writes.  It does not
    matter if the memory contains data.  (/me needs more coffee)
10/13 05:17:56 hiyuh
    yeah, "separated CEs and shared others" sound good to me though.
10/13 05:18:38 joe2371
    the data pins are not shared, though.  Address pins are.  But UB/LB/CE
    are not shared either.
10/13 05:21:26 joe2371
    the SRAM data sheet talks about "test load" only.
10/13 05:21:49 hiyuh
    I guess "when CE is disabled, it doesn't care other signals". why
    not shared address/data bus for that?
10/13 05:22:19 joe2371
    They want you to be able to read 32 bits at one time, I think.
10/13 05:22:31 hiyuh
    ah ok
10/13 05:23:25 joe2371
    they do have shared address, though.
10/13 05:23:40 hiyuh
    heh
10/13 05:25:25 joe2371
    Since the connection between SRAM and FPGA cannot be changed, then I
    think I can't think of anything I can do about the load from inside
    the FPGA.
10/13 05:26:08 joe2371
    s/I\ think\ I\ can't\ think\ of/I can't think of/
10/13 05:26:23 hiyuh
    well, the spec sheet should have typ val of rw timing by pic or
    table. so all what you do may be to constrain some timing of FPGA's
    output.
10/13 05:27:05 joe2371
    The SRAM is about 200 times faster than my CPU and is almost as fast
    as the FPGA.
10/13 05:29:02 joe2371
    My guess is that the SRAM will provide data long before the CPU
    tries to read it.  I hope I don't have too many timing problems.
10/13 05:31:57 hiyuh
    deskewing for I/O like feedback path may have many timing problems,
    too bad. ;p
10/13 05:33:10 hiyuh
    only for output has little problem of timing (like for D/A), iirc.
10/13 05:33:40 joe2371
    Do you know somewhere I can read more about this?
10/13 05:33:47 joe2371
    What should I search for?
10/13 05:35:02 hiyuh
    deskewing is common issue for FPGA design, see I/O and clock
    management section of your device's users guide.
10/13 05:35:12 joe2371
    oh, ok
10/13 05:35:20 hiyuh
    good luck :)
10/13 05:35:34 joe2371
    thanks. :-/
10/13 05:37:49 joe2371
    "skew" was not found in the documentation. :-/
10/13 05:39:32 hiyuh
    lol, what's your device?
10/13 05:40:08 joe2371
    Digilent starter board with spartan3
10/13 05:42:35 joe2371
    I found this in a referenced document "Digital Clock Managers also
    eliminate clock skew"
10/13 05:43:19 hiyuh
    yeah, DCM is a way for deskewing. :)
10/13 05:44:06 joe2371
    I have 4 of them, it looks like.
10/13 05:47:19 hiyuh
    well, maybe you want to use DCM_BASE or DCM_PS, I guess.
10/13 05:47:36 joe2371
    I'll look them up. Thanks.
10/13 05:47:51 hiyuh
    yw

Xilinx.ISE.karma--; /* MSVC++ runtime error!!1 */

今日のクラッシュ，もう何も言うまいて． :p
[Today's crash. All what I can say is only "WTF". :p]

JunkCode.karma++; /* csa_stim.c */

問題: このコードは何でしょう？ :9
[Q. This code for what? :9]

#include <stdio.h>
#include <stdint.h>
#include <string.h>

uint8_t do_csa(uint8_t *pa, uint8_t *pb)
{
 uint8_t a_xor_b, a_and_b;

 a_xor_b = *pa ^ *pb;
 a_and_b = *pa & *pb;

 *pa = a_xor_b;
 *pb = a_and_b << 1;

 return (a_and_b >> 7);
}

char *uint8_to_str(char *pstr, uint8_t q)
{
 switch (q & (uint8_t)0xF0) {
  case (uint8_t)0x00 : strcpy(&pstr[0], "0000"); break;
  case (uint8_t)0x10 : strcpy(&pstr[0], "0001"); break;
  case (uint8_t)0x20 : strcpy(&pstr[0], "0010"); break;
  case (uint8_t)0x30 : strcpy(&pstr[0], "0011"); break;
  case (uint8_t)0x40 : strcpy(&pstr[0], "0100"); break;
  case (uint8_t)0x50 : strcpy(&pstr[0], "0101"); break;
  case (uint8_t)0x60 : strcpy(&pstr[0], "0110"); break;
  case (uint8_t)0x70 : strcpy(&pstr[0], "0111"); break;
  case (uint8_t)0x80 : strcpy(&pstr[0], "1000"); break;
  case (uint8_t)0x90 : strcpy(&pstr[0], "1001"); break;
  case (uint8_t)0xA0 : strcpy(&pstr[0], "1010"); break;
  case (uint8_t)0xB0 : strcpy(&pstr[0], "1011"); break;
  case (uint8_t)0xC0 : strcpy(&pstr[0], "1100"); break;
  case (uint8_t)0xD0 : strcpy(&pstr[0], "1101"); break;
  case (uint8_t)0xE0 : strcpy(&pstr[0], "1110"); break;
  case (uint8_t)0xF0 : strcpy(&pstr[0], "1111"); break;
  default            : strcpy(&pstr[0], "????"); break;
 }

 switch (q & (uint8_t)0x0F) {
  case (uint8_t)0x00 : strcpy(&pstr[4], "0000"); break;
  case (uint8_t)0x01 : strcpy(&pstr[4], "0001"); break;
  case (uint8_t)0x02 : strcpy(&pstr[4], "0010"); break;
  case (uint8_t)0x03 : strcpy(&pstr[4], "0011"); break;
  case (uint8_t)0x04 : strcpy(&pstr[4], "0100"); break;
  case (uint8_t)0x05 : strcpy(&pstr[4], "0101"); break;
  case (uint8_t)0x06 : strcpy(&pstr[4], "0110"); break;
  case (uint8_t)0x07 : strcpy(&pstr[4], "0111"); break;
  case (uint8_t)0x08 : strcpy(&pstr[4], "1000"); break;
  case (uint8_t)0x09 : strcpy(&pstr[4], "1001"); break;
  case (uint8_t)0x0A : strcpy(&pstr[4], "1010"); break;
  case (uint8_t)0x0B : strcpy(&pstr[4], "1011"); break;
  case (uint8_t)0x0C : strcpy(&pstr[4], "1100"); break;
  case (uint8_t)0x0D : strcpy(&pstr[4], "1101"); break;
  case (uint8_t)0x0E : strcpy(&pstr[4], "1110"); break;
  case (uint8_t)0x0F : strcpy(&pstr[4], "1111"); break;
  default            : strcpy(&pstr[4], "????"); break;
 }

 return pstr;
}

int main(int argc, char *arcv[])
{
 uint8_t a, b;
 uint8_t a_add_b;
 uint8_t a_csa, b_csa;
 uint8_t n_csa;
 char a_str[] = "00000000";
 char b_str[] = "00000000";

 for (a = 0; a < (uint8_t)0x80; a++) {
  for (b = 0; b < (uint8_t)0x80; b++) {
   a_add_b= a + b;

   a_csa = a;
   b_csa = b;
   n_csa = 0;
   do {
    printf(" CSA(%s, %s)",
     uint8_to_str(a_str, a_csa),
     uint8_to_str(b_str, b_csa));
    do_csa(&a_csa, &b_csa);
    n_csa++;
    printf(" = (%s, %s) ... %d\n",
     uint8_to_str(a_str, a_csa),
     uint8_to_str(b_str, b_csa), n_csa);
   } while (b_csa != (uint8_t)0x00);

   printf("%02X | %02X || %02X | %02X || %s\n",
    a, b, a_add_b,
    a_csa, (a_add_b != a_csa) ? "NG" : "OK");
  }
 }

 return 0;
}

Xilinx.ISE.karma--; /* Stack corrupted!!1 */

ISEが低品質過ぎます，仕事じゃなかったらこんなブツは速攻でabandonだな． :(
[ISE really suXX0rz!!1 All why the hell I can not abandon this crap is b/c it's my job ATM.]

何してたかと言うと，200bitsのバスを隣のFPGAに突っ込むので，ボード上でのタイミング制約
を課す為に物理パッドの論理集合を作っていた．
どうみても固定長配列での集合演算ルーチンです，本当にありがとうございました． :P
[So what I did is to create logical group from physical pads to constrain
bus I/O timing between 2 FPGAs.
That *is* fsckin' set operation routines w/ fixed length array, thank god. :p]

修正：
slangだらけの英語追加．
[Add fskin' my Eng'r'ish.]

GentooJP.NomiKai++; /* OSC 2007 Fall */

京急蒲田の辺りでOSC 2007 Fallでした．
[OSC 2007 Fall @ Keikyu-Kamata.]

今回は開始早々から遥々福井県からmasayukoさん達が参加してくれました．
masayukoさんはGentooJP Java leadな方です，多分． :p
[Dudes came from Fukui-pref. masayuko, AKA GentooJP Java lead... J/K. :p]

展示の方はamd64, x86, ppcのノートPC三台で，全てがタイル型ウィンドウマネージャ
(awesome x2, wmii x1)と言う基本構成で，matsuuさんはデモ用にLive CD 2007.0
も動作させていました．両隣のNetBSDの中の人達やsuseの中の人達とムニャヘニャしつつ，
「にーはお」と言う変な中華料理屋でのお昼を挟んで展示を見に来て頂いた人達にebuildの中身
を説明したり，SH*な人にアドバイスしたりとか．
[Exhibiting w/ 3 laptops. amd64, x86 and ppc, all laptop is running w/ tiling
window manager (awesome x2, wmii x1)． Of course, we did w/ Live CD 2007.0
to demo. Talking w/ NetBSD and suse dudes sometimes. Lunch at "Ni-Hao".
And I've explained ebuild inside or minor arch maintenance policy for FreeBSD
and SH* guys.]

夕方からは飲み会．とりあえず，idaniさんの案内で蒲田の手羽先なお店に入った．
trombik先生のOpenBSD節を基本に，レイヤの高いお話などなどが展開されておりましたので，
レイヤの低い私には理解出来ない所が多々ありましたが，そんな事は気にしません． :D
[OSC was over, then we went to do NomiKai, first one is Tebasaki by idani.
Trombik talk passionately about OpenBSD, and something about higher layers'
that's what I can not understand a bit, but it's not problem. :D]

で，trombik先生オススメ(?)の冥土喫茶に突撃したが，満席と言う罠．
「いってらっしゃいませ，ごしゅじんさま」ってマジで言うのか． :DDD
[Then, trombik leads to his favorite Maid-Cafe.
But all the tables have been taken.
"itte rassyai mase, goshujin-sama" really rock0rz. :DDD]

更に，お好み焼き屋で二次会．
北海道vs福井県とか，日本はもうダメだとか，でも日本のお笑いには将来性があるとか，
スカパーのディスカバリーチャンネルを見ていると仕事にならねーとか．
[Second one is Okonomi-Yaki.
Hokkai-Do vs Fukui-Pref, Japan has no IAP but Japanese comedy has IAP,
Discovery channel of sky prefect TV made us sometimes "WTF".]

masayukoさんは日曜日にお子さんの運動会があるので，10時位に切り上げ．
上野まで御一緒させてもらいました．それから夜行列車で福井まで戻るそうで，大変だ！
乗り換えギリギリまでjavaの話とかをしていたので慌しくなってしまいましたが，
また話が出来ればいいですね． ;)
["Time to call it a night", at about 10:00 PM.
I came back w/ masayuko till the train arrived at Ueno.
We've been talking about java or something, so masayuko almost
missed its stop, though. Let's get together soon. :)]

LX200 = pow(10, 6) * YEN; pOSC->bugz(eLIVE);

今，遊んでいるVirtex4なブツ．
[This is Virtex4 board I'm codin' for.]

Virtex4はLX, SX, FXの三種類，それぞれロジック，DSPとメモリ，I/Oに特化している（らしい）．
LX200はLXシリーズの最高クラスのブツ．で，こいつLX200が四つ載っている．
LX200は百万円/個だとボスが言っていた．つまり，ボード一枚の部品代で四百万円．
そんなんが八枚もこの青い箱の中に入っている． :DDD
[Virtex4 has 3 series LX, SX and FX. They are for logic performance,
DSP and memory, I/O oriented. LX200 is highest one of LX series.
This board has 4 LX200s. LX200 costs about 1000000 yen, my bosses said.
Well, so 8 boards are in this blue box, so WTF? :DDD]

で，その蝶高級ボードに突っ込む予定のヘタレVHDLはこんな感じでSLOCが膨れ上がっています． :)
[An VHDL test sources for t3h boards are being now bloated by me. :)]


ところで明日はOSCです．bugdayな感じでテキトーにやりますのでヒマな方はお越し下さい． :)
[BTW, 10/6 is OSC, it will be bugday. Let us fix0rz bugz? :)]

I HAS 1337 VHDL. LOL!!1

この野郎，思わず爆笑しそうになったじゃねーか！！１ :DDD
[WTF, I'D LOLZ!!1 :DDD]

goto PinAssignHell;

イルカよ，お前が最後の頼りだ！１１ :DDD
[OH MY DOLPHIN, PLZ HALP ME!11 :DDD]

buildOK(mfdlibm) ? me.karma++ : me.karma--;

やっと-std=c99 -pedantic-errorsでビルド出来る様になった． :)
なお，テストはしていないので，動作は保証出来ません． :p
[w00t, mfdlibm can be build w/ -std=c99 -pedantic-errors. :)
But IT JUST WORKS(tm), is not tested yet. :p]
mfdlibm mercurial repository

Xilinx.Virtex4.UCF.karma--; fdlibm.lvalue.karma--;

ブツの製品検査の為にVirtex4が四つほど載っているボードのテスト用ファームウェアをムニャる．
[Poking Virtex4 x4 board w/ its firmware for inspection.]

ボードは全部で8枚，Virtex4が1個あたり800~900本ほど最上位層のVHDL entityから物理配線
制約を課すUCFなファイルを生成，と言うか改造．
今回使用するブツは改版後のモノで，改版前のUCFなファイルをあちこち修正する必要があった．
40ページの改版前の回路図と改版後の回路図と12時間ほど格闘．
で，やっと内部配線のチェックが出来るくらいまで修正した． :)
[Planning to use 4 boards for t3h B2. Each Virtex4's top VHDL entity has about
800 ~ 900 bits signal. So I'd have to modify the previous UCF file to constrain
physical pin assign. Gazing previous and current schematics which has A4 x40 in
about 12 hours. Finally, IT JUST WORKS(tm). :) But it's only for internal
connections inspection ATM.]

fdlibmを引き続きムニャっている．
[Poking fdlibm, as well.]

#if __BYTE_ORDER == __LITTLE_ENDIAN
 #define __HI(x) *(1 + (int*)&x)
#elif __BYTE_ORDER == __BIG_ENDIAN
 #define __HI(x) *(int*)&x
#endif

...

double z;
__HI(z) ^= 0x80000000;

...

コイツぁ，ひどいlvalueですね． ;p
こんなのを見た時はコイツを引用したくなる． :DDD
[ZOMG, how nice lvalue abusing... ;p
Well, this nice pic is kinda my feeling. :DDD]

Xilinx.Virtex4.DSP48.karma--;

AGC B2 forkを予定動作クロックで動く様にグローバルクロック制約付きでISEにてモニョる．
具体的に言うと，突っ込む予定のVirtex4なFPGAの中にあるDSPになる様に結合乗加算やら
結合加乗算をFFで分離したり，運用で対処出来る範囲でコンパレータのbit幅を縮めたり．
[Poking AGC B2 fork w/ working (planning) global clock on fscking ISE.
So, isolate fused multiply-add/add-multiply, or shrinking comparator
bit length to push into Virtex4's internal DSP.]

で，結局，受信側PHY下位層で動くブツは，予定動作クロック128MHzに対して130MHz．
送信側PHY下位層で動くブツは，予定動作クロック256MHzに対して，141MHz．
やっぱ，256MHzは無理やん．中のDSPは500MHzで動くとか言っとるらしいけど，
たぶんハッタリと見た． :DDD
[Finally, I did the one which function at where lower layer than reception
PHY will function w/ 130MHz (planning clock is 128MHz), and the one at where
lower layer than transmission PHY will function w/ 141MHz (planning clock is
256MHz). Bah, it might be impossible to function w/ 256MHz to me. *stab*.
T3h fscking DSP won't function w/ 500MHz, unlike t3h spec saz.
/me failz. :DDD]

つーか，後者は配線遅延が既に六割を越えてるし，オーバーサンプリング前のクロックで
動かす方向で検討せねばならんね，コイツは． :p
[Well, the latter's route delay takes over six out of ten. There is no way to
make it capable, I guess. I should reconsider to make it function at where
pre-oversampling domain. :p]

Bump("x11-base/xorg-x11", 7, 3); CodeCleanUp(fdlibm);

x11-base/xorg-x11-7.3が入ったので，速攻でemerge．
で，x11-drivers/synapticsのbugを喰らう．
そこで困った時のbugzie，これで直る，多分． :p
bug #191924
[Emerged x11-base/xorg-x11-7.3. Eh, x11-drivers/synaptics sucks.
Kk, do dig bugzie, will fix0r soonish!!1 :p
bug #191924]

fdlibmをモニョっている．SoftFloatと合わせて，IEEE 754{,r}もチェックすれば，
あなたも明日から"ばいなりー"な浮動小数点生活をenjoy出来ます． ;)
[Poking fdlibm now. See also SoftFloat and IEEE 754{,r} for enjoy
your "binary floating-point" life. ;)]

CXX.karma--;

sys-devel/gcc-4.2.0がbuggy過ぎるのとDもやりたくなってきたので，
USE=multislotでtoolchain overlayを使ってSLOT=4.1, 4.2共存の上，
4.3のalphaを突っ込んだが，ICEやらsanity check errorが止まらなーい．
やっぱりCXXはアレ気だ． :DDD
[sys-devel/gcc-4.2.0 is kinda buggy, and am interested in D.
So, now time to USE=multislot w/ toolchain overlay.
I did emerge SLOT=4.1, 4.2, and 4.3 alpha. Yay, ICE and sanity
check error floods!!1 Oh dear, CXX su^H^Hrocks!11 :DDD]

で，具体的にどれぐらいアレかと言うと，これくらい． :p
[Eh, if you'd like to see how CXX su^H^Hrocks, see this. :p]

ReMeasureSLOC(&AGC_B2Fork);

例によってAGC B2ForkのSLOCを晒し上げ．
[Here is AGC B2Fork's SLOC trend to revision 124.]

前回の1.5倍位に膨れ上がっているのはテストベンチを突っ込んだから．
[Add bunch of test bench made total SLOC x1.5 bloated.]

• revision 100辺りまでAdd draft test benches．
• revision 120辺りまでBunch of fix for the benches．
• revision 124で増えているのはテストベンチをまとめるラッパーを突っ込んだから．

IfGenerateStatement.karma--;

仕様なのは知ってるけど，VHDLのif-generateはなんでelseが使えないんだ？ :(
[VHDL's if-generate statement kinda sux. :(]

:
:
entity FOO is
 generic (
  :
  nDW    : integer 3 to integer'high := 12;
  nDELAY : integer 0 to integer'high := 2**8 - 1;
  nNL    : integer 3 to integer'high := 2**4 - 1;
  :
 );
 port (
  :
  iCLR  : in  std_logic;
  iDIN  : in  std_logic_vector(nDW-1 downto 0);
  oDOUT : out std_logic_vector(nDW-1 downto 0);
  :
 );
end FOO;
:
architecture RTL of FOO is
:
:
 constant cZEROxDW : std_logic_vector(nDW-1 downto 0) := (others => '0');
 type tDMEM is array (0 to nNL-2) of std_logic_vector(nDW-1 downto 0);
 signal rDMEM : tDMEM := (others => cZEROxDW);
:
:
begin
:
:
 G_0FF_DELAY : if (nDELAY = 0) generate
  oDOUT <= cZEROxDW when (iCLR = '1') else iDIN;
 end generate;

 G_1FF_DELAY : if (nDELAY = 1) generate
  P_1FF_DELAY : process (iCLK)
   if (iCLK'event and iCLK = '1') then
    if (iCLR = '1') then
     oDOUT <= cZEROxDW;
    else
     oDOUT <= iDIN;
    end if;
   end if;
  end process;
 end generate;

 G_nFF_DELAY : if (nDELAY > 1) generate
  P_nFF_DELAY : process (iCLK)
   if (iCLK'event and iCLK = '1') then
    nADDR <= (nADDR + 1) mod (nNL - 1)
    if (iCLR = '1') then
     for v in rDMEM'range loop
      rDMEM(v) <= cZEROxDW;
     end loop;
     oDOUT <= cZEROxDW;
    else
     rDMEM(nADDR) <= iDIN;
     oDOUT        <= rDMEM(nADDR);
    end if;
   end if;
  end process;
 end generate;
:
:
end RTL;

それからModelSim XE 6.2gがこうやって書くとmultiple sourcesだと勘違いしやがる．
coverage機能がどうのこうのと言う前に嘘の警告を出さない様にしてくれ． :P
[And ModelSim XE 6.2g also sux, it'd buzz me about this code has multiple
sources, WTF. To fix wrong buzz should be given priority over to improve
coverage features, IMHO. :p]

修正: "type tDMEM us" -> "type tDMEM is"
[FIX: "type tDMEM us" -> "type tDMEM is"]

MeasureSLOC(&AGC_B2Fork);

以下，AGC B2Forkの状況を晒し上げ．
[Here is AGC B2Fork's SLOC trend to revision 70.]

• revision 5辺りまででadd FIXMEs．
• revision 15辺りまでdelete unrelated provious' comments．
• revision 30辺りまでexport internal generics．
• revision 50辺りまでvarious fixes for pipeline calculations.
• revision 50辺りでinternal statemachine rewrite.
• revision 70辺りまでsanitize entities' name．

IsCppNewbie(&me);

ビミョーに仕事をサボりつつ，STLport関連のページとかをホゲホゲ．
個人的にC++は食わず嫌い，実際にブツを作ってみると果たしてどうなるんか少し試す事にした．
以下，メモ．
[Going on a jaunt STLport. I'm not C++ haX0r, but I don't line C++. But tasting is always not bad idea. The following is a part of diff C to C++ for me.]

• line comment
• default value of function's argument
• overloaded function
• dynamic memory
• anonymous unions
• class
• constructor, destructor
• overloading operater
• this
• polymorphisms
• templates
• name spaces
• exception
• type casting

単純なブツなら副作用に気を付けてCで#define使って実装してしまいそうだとか，そんな書き方は怠け過ぎだろとか思ったりするけど． :p
[Some of the aboves looks to be able to be implemented by #define macro magiX. Or looks too lazy codin' stuffs, blah blah blah... :p]

agc = fork(); read(CoreConnect, &me, sizeof(ALL));

新しいRFなブツの為にAGCをfork(2)．
この前のRFなブツは色々ダメダメだったのでPHY下位層はAGCも含めてかなりアレ気だったが，
今回は楽かもしれないと淡い期待をしてみる．今の所，心配なのは前回のブツの1.5倍位の
クロックで動かすつもりだという事と例のブツ一式でマンションが買える値段（ボス談）の
装置だって事だけ． :p
[Fork(2) for new RF module. The previous one really su^H^Hrocks,
it beats entire lower-than-PHY layer's consistencies includes AGC.
However, new one looks sane characteristics, IMHO. ATM, what I'm a
little worried about is it will function w/ x1.5 faster clock than previous
one and it's worth a lot of money to buy some condos. :p]

PA-RISCなブツも一通り目を通したので，ISA関連はヒトマズ終了．
次はon-chip interconnectとperipheral．
取り敢えず，CoreConnectが分かり易そうなのでコイツを読むべす． :)
[Skimed through PA-RISC's, to read something related ISA will be suspended.
Next is on-chip interconnect and peripheral. Well, CoreConnect tastes good
to me. :)]

ForcedVacation(&me, 7 * WeekDay);

例のP4が終わり，その罪で今日(2007/07/14)から強制休暇一週間の刑に服役． :P
尚，今週末から来週前半は実家に戻る為，IP unreachableになります．
[Finally, I will serve 7 weekdays in forced vacation. :P
And I'd have to be IP unreachable at this weekend and few next weekdays
b/c returning to my hometown.]

以下，ここで音信不通だった間にムニャヘニャした主なモノ．
[Here is some stuffs what I was poking.]

multitalk 1.2.1のebuild及びパッチを作成．
で，「パッチ作ったから次のreleaseでマージじやがれ」なEng'r'ishなメールを送信．
「そんなデカいif文はありえんので．switch文にdefaultを足すよ」
「ハードコードされているpathはディストリビューション依存だからだめ」
つーダメ出し以外は全部マージしてくれたっぽい． :)
[ebuild and patches for multitalk 1.2.1.
And I e-mail-ed to submit these patches to merge upstream w/ my Eng'r'ish.
Upstream dev replied like
"Big if statement is crazy, I'd like to add default case to the switch statement."
"To change the hard-coded path is a bit of distribution specific, I won't merge."
So, other ones are fully merged. :)]

長らくbugzieで熟成されたghdl 0.26が公式ツリーに入った．
#gentoo-ppc@irc.freenode.netでppc herdのmabiを突っついて，
「~ppcにキーワードしてーな」
と先週末位にお願いしたのにまだ~x86しかキーワードされてねーじゃん！ :(
まぁ，俺様overlayの方にも残っているのでどーでもいいと言えばどうでもいいが．
[bugzie's ghdl 0.26 pwns now in official tree.
At #gentoo-ppc@irc.freenode.net, I've poked one of ppc herd, mabi
to add ~ppc to the offcial ebuild though.
That promise would be done at last weekend, but not ~ppc even now! :(
Well, but that's OK to me b/c the old one still stuffed my own overlay.]

Alpha Architechture Handbookを一通り読んだ．
PowerとMIPSのブツも読んだし，次はPA-RISC．
[Alpha Architechture Handbook was pwnt.
Power and MIPS ones were already pwnt.
So next one is PA-RISC.]

他にも色々やった気がするけど，忘れた．忘れたって事は大した事ではないので割愛． :P
[Well, I can't remember other stuffs correctly. So I guess it's not so important ones. :P]