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#vhdl@irc.freenode.netでMemory I/Fなお話．
[Here is a snippet log #vhdl@irc.freenode.net. The subject is a memory I/F.]

10/13 04:14:34 joe2371
    Are questions about schematics portable between languages and
    software?  I'm trying to find out the correct way to connect one
    signal to two FPGA pins.  Do I want to treat my signal as a 1-bit bus
    and put two taps on it?  I thought that bus taps required the nets
    on both sides to have compatible names (eg: Addr(19:0) -> Addr(15)
    and not Addr(19:0) -> Foo).  Is this splitting best done in the pin
    assignment file (.ucf) ?
10/13 04:28:44 hiyuh
    depends on transfer speed, imho.
10/13 04:32:33 hiyuh
    e.g. I'm now working 8 boards (each one has 4 virtex4).
10/13 04:33:21 hiyuh
    each virtex4 will input/output from/to others, the data syncs 128MHz
    via simple parallel bus.
10/13 04:33:26 hiyuh
    the output to outside of the board will be syncs 256MHz as LVDS.
10/13 04:33:38 hiyuh
    sample pic is http://dev.gentoo.gr.jp/~hiyuh/misc/V4LXB.jpg
10/13 04:35:12 hiyuh
    reference clock's accuracy and deskewing of sync clock is also PITA.
10/13 04:35:32 hiyuh
    s/is/are/
10/13 04:38:47 joe2371
    That's a nice looking board.  The Virtices have fans on them?
10/13 04:39:58 hiyuh
    yup
10/13 04:41:38 hiyuh
    the left side one is japanese tobacco box, btw.
10/13 04:41:59 joe2371
    With the letter C ?
10/13 04:42:10 hiyuh
    yeah
10/13 04:43:12 joe2371
    pretty neat.  I'd hate to think what it costs.
10/13 04:44:27 joe2371
    Do tools exists that can map a design across multiple chips
    automatically?
10/13 04:45:51 joe2371
    ...basically treating four FPGAs like one larger one, I mean.
    The more I think about it, the less likely I imagine that is.
10/13 04:46:02 hiyuh
    my bosses said, one Virtex4 LX200 (the best one of Virtex4 LX series)
    will costs about 1000000 yen. but it should depends on quantities
    of order, I guess. :p
10/13 04:47:05 joe2371
    It's something like 1000 yen to the dollar, I think.  Ouch.
10/13 04:47:43 hiyuh
    I dunno that neat tool which automatically map it to them.
10/13 04:48:29 joe2371
    I guess if they are Virtex chips, you are stuck with Xilinx tools.
10/13 04:49:39 hiyuh
    yeah, it's kinda corporate (or project's?) policy, maybe.
10/13 04:50:48 hiyuh
    so I can take a screenshot of fsckin' ISE crashing per working day. :p
10/13 04:51:15 joe2371
    Only once per day?  ISE crashes sometimes 3-5 times on me.
10/13 04:51:50 joe2371
    At least it recovers my work OK. (so far)
10/13 04:52:49 hiyuh
    I'd have to treat that crap *gently*, b/c it's my job atm. :p
10/13 04:55:31 hiyuh
    well, using same name in sch and logical vhdl design is a bit of
    difficult, if it's a dead-lined project.
10/13 04:57:03 hiyuh
    and ucf craps are not only for constraining the pin assign.
10/13 04:57:40 hiyuh
    splitting them to ucf is a good way to go, though.
10/13 04:57:44 joe2371
    Ok. My lab homework assignment is to create a 1MB memory controller
    with only 14 address pins.  I am trying to connect one signal to
    two memory chips (same signal, different pins).
10/13 04:58:04 hiyuh
    heh
10/13 04:58:09 joe2371
    I created that 1-bit bus with two taps.
10/13 04:58:16 joe2371
    I don't know if it works, though.
10/13 05:00:58 hiyuh
    have you consider about the memories' I/F, driving load, or something?
10/13 05:01:19 hiyuh
    s/consider/considered/
10/13 05:02:16 joe2371
    oh, no.  I am still experimenting with my initial concept for
    the design.  I don't know what difficulties to expect.
10/13 05:03:31 hiyuh
    ah, ok. then first step is to gaze the memories' spec sheet, I
    guess. :)
10/13 05:03:49 joe2371
    The documentation for the board did not talk about driving load
    that I can remember.  It just says which pins of the FPGA are tied
    to which pins of the SRAMs
10/13 05:04:04 joe2371
    I have the specs for the SRAM here
10/13 05:05:17 hiyuh
    SRAM? then it doesn't need to be refreshing, right?
10/13 05:05:25 joe2371
    right
10/13 05:05:39 joe2371
    yes, I am lucky it is SRAM
10/13 05:06:18 joe2371
    But I am unlucky I have only 14 address bus pins connected.
10/13 05:07:50 hiyuh
    SRAM's address is 14bits?
10/13 05:08:02 hiyuh
    or you have only 14bits on FPGA to specify SRAM's address but SRAM's
    address is not 14bits?
10/13 05:09:38 joe2371
    no, 18 bits for a 16-bit memory location, plus upper byte and lower
    byte pins, plus there are two chips.  So SRAMs actually have 20-bit
    address (of bytes).  But I have a CPU which has only 14 address pins
    connected to the FPGA.
10/13 05:10:12 joe2371
    I want to use the LSB of the address to select upper/lower byte.
    And LSB+1 to select SRAM0/SRAM1.
10/13 05:10:34 joe2371
    the missing MSBits are provided from a register tied to a port.
10/13 05:11:16 joe2371
    but I need to connect the LSB and LSB+1 to four pins.
10/13 05:11:28 hiyuh
    oic
10/13 05:14:44 joe2371
    I just thought of something.  If chip enable is off, these SRAMs
    go to low power mode.  Maybe I should organize my pins differently
    so that I will use less power when the memory is less than half
    full... Hmmm... I'll think about that.
10/13 05:16:22 joe2371
    I think it means changing one line of HDL.  Then I can say my design
    not only works, but is also efficient. :-)
10/13 05:17:43 joe2371
    Nevermind.  CE only goes high on reads and writes.  It does not
    matter if the memory contains data.  (/me needs more coffee)
10/13 05:17:56 hiyuh
    yeah, "separated CEs and shared others" sound good to me though.
10/13 05:18:38 joe2371
    the data pins are not shared, though.  Address pins are.  But UB/LB/CE
    are not shared either.
10/13 05:21:26 joe2371
    the SRAM data sheet talks about "test load" only.
10/13 05:21:49 hiyuh
    I guess "when CE is disabled, it doesn't care other signals". why
    not shared address/data bus for that?
10/13 05:22:19 joe2371
    They want you to be able to read 32 bits at one time, I think.
10/13 05:22:31 hiyuh
    ah ok
10/13 05:23:25 joe2371
    they do have shared address, though.
10/13 05:23:40 hiyuh
    heh
10/13 05:25:25 joe2371
    Since the connection between SRAM and FPGA cannot be changed, then I
    think I can't think of anything I can do about the load from inside
    the FPGA.
10/13 05:26:08 joe2371
    s/I\ think\ I\ can't\ think\ of/I can't think of/
10/13 05:26:23 hiyuh
    well, the spec sheet should have typ val of rw timing by pic or
    table. so all what you do may be to constrain some timing of FPGA's
    output.
10/13 05:27:05 joe2371
    The SRAM is about 200 times faster than my CPU and is almost as fast
    as the FPGA.
10/13 05:29:02 joe2371
    My guess is that the SRAM will provide data long before the CPU
    tries to read it.  I hope I don't have too many timing problems.
10/13 05:31:57 hiyuh
    deskewing for I/O like feedback path may have many timing problems,
    too bad. ;p
10/13 05:33:10 hiyuh
    only for output has little problem of timing (like for D/A), iirc.
10/13 05:33:40 joe2371
    Do you know somewhere I can read more about this?
10/13 05:33:47 joe2371
    What should I search for?
10/13 05:35:02 hiyuh
    deskewing is common issue for FPGA design, see I/O and clock
    management section of your device's users guide.
10/13 05:35:12 joe2371
    oh, ok
10/13 05:35:20 hiyuh
    good luck :)
10/13 05:35:34 joe2371
    thanks. :-/
10/13 05:37:49 joe2371
    "skew" was not found in the documentation. :-/
10/13 05:39:32 hiyuh
    lol, what's your device?
10/13 05:40:08 joe2371
    Digilent starter board with spartan3
10/13 05:42:35 joe2371
    I found this in a referenced document "Digital Clock Managers also
    eliminate clock skew"
10/13 05:43:19 hiyuh
    yeah, DCM is a way for deskewing. :)
10/13 05:44:06 joe2371
    I have 4 of them, it looks like.
10/13 05:47:19 hiyuh
    well, maybe you want to use DCM_BASE or DCM_PS, I guess.
10/13 05:47:36 joe2371
    I'll look them up. Thanks.
10/13 05:47:51 hiyuh
    yw