wmii.karma++; /* Cygwin/X */

Virtex4 LX200 6個分のボードレベルシミュレーション中，暇だったのでテキトーにportingしてたら，なんか動いたらしい． :DDD

EGIT_TREE="1337" emerge x11-drivers/xf86-video-nouveau

　ボブ「やあ，ジョニー，聞いてくれよ．」
ジョニー「なんだい，ボブ．」
　　ボブ「最近，nouveauがGallium3Dな感じでイケてるじゃん．」
ジョニー「mesa/mesaのmasterにも入ったしね．」
　　ボブ「そうそう．」
ジョニー「xf86-video-nvも粛正されたらしいって聞いたよ？」
　　ボブ「うん，x11 overlayの方は何気にGallium3D capableなんだ．」
ジョニー「へー．」
　　ボブ「で，件のgit live ebuildを調子に乗ってガンガンemergeしてたんだけど．．．」
ジョニー「それで？」
　　ボブ「Xが起動しなくなっちゃたんだよ！」
ジョニー「あら，まあ．」
　　ボブ「なぁ，どうしたらいい？」
ジョニー「んー，upstream dev的にはgit bisectしろって言いたい所だけど．」
　　ボブ「あー，やっぱり？」
ジョニー「今までは動いてたんだよね？」
　　ボブ「うん．」
ジョニー「とりあえず，動けばいいの？」
　　ボブ「うん．」
ジョニー「DRMとDRIとDDXのどれが壊れたの？」
　　ボブ「drm.koとnouveau.koはキチンとmodprobeされてる．dmesgで確認したよ．」
ジョニー「じゃあ，DRMは大丈夫そうだね，mesa/drmは最近更新されてないし．」
　　ボブ「DRIならruntimeでswrastにfallbackするはずだから，これは保留だね．」
ジョニー「/var/log/Xorg.0.logは何て言ってるの？」
　　ボブ「なんかBIOSがどうのこうのってメッセージを出して死んでるみたい．」
ジョニー「それ，先頭にNOUVEAU([0-9]*)ってのが付いてる？」
　　ボブ「うん．」
ジョニー「きみ，ppc32だったね？」
　　ボブ「うん，x86が嫌いだからね．」
ジョニー「多分，DDXのnv_bios.cが壊れたんだね．」
　　ボブ「そうなの？」
ジョニー「最近，KMSやwfb関連で色々手が入ってるのさ！」
　　ボブ「へー．」
ジョニー「勘でbisectするとbad commitはこれかな？」

bios: use image from PRAMIN in preference to PROM on NV50

　　ボブ「じゃあ，無難にこの辺りに戻せばいいのかな？」

Add DVI-A output info for Mac card missing bios tables (#21273)

ジョニー「試してみよう．」
　　ボブ「どうやるんだい？」
ジョニー「こうさ！」

EGIT_TREE="b7e3306ddc3693699f6f9de7b22913ee22ed31ed" \
    emerge --oneshot =x11-drivers/xf86-video-nouveau-9999

　　ボブ「なるほど，EGIT_TREEで特定のcommit revisionを指定してあげればいいんだね．」
ジョニー「うん，x11-drivers/xf86-video-nouveauはgit.eclassを使ってるからね．」
　　ボブ「と言うか，EGIT_TREEなのにtree revisionじゃだめなの？」
ジョニー「commit revisionじゃなきゃだめだよ」
　　ボブ「なんで？」
ジョニー「gitはUIがbad designだからじゃない？　平たく言えば，仕様かな？」
　　ボブ「あー，仕様なら仕方ないかー．」

　　　　＝＝＝ emerge実行 & X再起動 ===

　　ボブ「おー，ジョニー，動いたよ！」
ジョニー「じゃあ，またricerな生活を満喫出来るね！」
　　ボブ「ああ，やっぱりGentooは最高だね！」

# 2009/06/17 ちと修正． :)

MeasureSLOC(&AL9); /* 2009/05 */

AでLで9なdiffstat，5月分．
[diffstat for AL9, for 2009/05.]

 b/bench/BENCH_CLDPCDOP.vhd      |  364 +++++++++
 b/bench/BENCH_LDPCTX.vhd        |  720 +++++++++++++++++++
 b/bench/LDPCTX_MEM.vhd          |  191 +++++
 b/bench/MT48LC16M16A2x1.vhd     |  234 ++++++
 b/stim/STIM_FCOD_DATA.vhd       |  217 +++++
 b/vhdl/RX_LX_FEBE.vhd           |  602 ++++++++++++++++
 bench/BENCH_LDPCDDB.vhd         |   84 +-
 bench/BENCH_LDPCEDB.vhd         |    5 
 bench/BENCH_SB.vhd              |  170 +++-
 bench/BENCH_TSR_CLK.vhd         |   44 -
 bench/METABENCH_LDPCDDB.vhd     |   58 -
 bench/METAMETABENCH_LDPCDDB.vhd |   12 
 vhdl/CLDPCDOP.vhd               |    5 
 vhdl/CSSSTM.vhd                 |    3 
 vhdl/ELDPCDII.vhd               |  110 +-
 vhdl/FP1_LDPCTX.vhd             | 1474 +++++++++++++++++-----------------------
 vhdl/FP2_LDPCTX.vhd             | 1026 +++++++++++++++------------
 vhdl/FP3_LDPCTX.vhd             |  130 ++-
 vhdl/FP4_LDPCTX.vhd             |  132 ++-
 vhdl/LDPCD-stub.vhd             |    4 
 vhdl/LDPCD.vhd                  |   85 +-
 vhdl/LDPCE-stub.vhd             |   30 
 vhdl/LDPCE.vhd                  |   60 +
 vhdl/LDPCEDB.vhd                |    6 
 vhdl/PN_BLOB.vhd                |   46 -
 vhdl/SELDPCDIIM.vhd             |    6 
 vhdl/TSR_CLK.vhd                |  149 ++--
 vhdl/TX_SRC_MUX.vhd             |    7 
 vhdl/TX_SX_FEBE.vhd             |  157 ++--
 vhdl/UDACCUM.vhd                |  137 ++-
 30 files changed, 4485 insertions(+), 1783 deletions(-)

やっぱ，10kSLOC逝ってないNE!!1 :DDD
残るは受信側なのでもう一息．
[ZOMG, under 10kSLOC AGAIN!!1 :DDD
'kay, rest parts I have to code is RX's.]

downstream = dup(upstream);

s9fesのさきっぽを追っかけてるらしいdebianな人が「オレのとdupってるぜ！！1」とか言うのでその返事．

きっと親切心でメールをくれたんだと思うんだけど，オレはさきっぽを追っかける事自体が目的みたいなもんだからdupしてても一向に構わんのだけどなぁ．
結局upstreamの中の人が気に入ればdownstreamのchangesetはupstreamにmergeされて，結果全てのdownstreamに還元される訳だし，DSCMってそう言う為のモノじゃねぇの？

つーか，なんでみんなgit使ってんだよ！！1 :DDD

Me -= Blood; Me +=Coffee; Me += GyouZa;

高専時代の知り合いから電話があった．
オレと違って大学に編入した後で修士まで行ったらしく，しかもオレの今の仕事の分野に近いトコロをゴニョっていた様で妙に話が合って蝶意外．

が，メインはそっちじゃなくて，高尚なものではないけど抽象的な人生相談(?)の様なモノだった．
例の如く不況の煽りを受けて修士を出てから就職した会社のある部門が無くなるそうで．
「オレはエラくもないし，職は斡旋出来ないぜー」とか言ったら，もう幾つか内定は貰っているが，いい機会だから色々考えたいんだとか．
で，高専時代でもオタク全開だったオレが今は何をやらかしているのかとか聞きたかったらしい．
ふむふむ．．．ぬるへそ，ぬるへそ．．．
．．．って，オタクのまんまに決まってんじゃん，変わりゃしねぇよ． :DDD

つー訳で，オレはヒキコモリなハズなんだが，土日連続で外出すると言う異例の事態に．
駅で待ち合わせをしている間のヒマつぶしに献血して，合流してから"どとぉる"なコーヒーと餃子メインの店のメシをゴチになってきた．
オレの話が参考になったかどうか分からんけど，彼はオレよりずっと英語出来るし，スゲェイケメンなので大丈夫じゃね？ :DDD

別れ際，「今度就職祝いしてくれー」とか言ってた．
今日のお返しにメシくらいおごってやるさ．
まぁ，頑張れや． :)

HikiKomori | ~HikiKomori

会社に案内が来てて，ボスが「暇なら行けば？」みたいな事を言っていたので，俺はひきこもりなはずなんだが，今日はNHK放送研究所の技研公開に行ってきた．
休日なので一般の人が蝶いっぱい．

見栄えのするブツの方に人が集まってたけど，仕事でお手伝いさせてもらったブツの展示をメインに見てきた．
アンテナの受信信号を並列に記録するHDDレコーダのお化けを拵えてリアルタイム復調してた，地味にすげぇ． :DDD

それにしてもあの辺は雰囲気がおしゃれ(?)過ぎて，なんか落ち着かない．
んー，どうしたもんかなぁ．

USE=-gold emerge sys-devel/binutils

　ボブ「やぁ，ジョニー，聞いてくれよ．」
ジョニー「なんだい，ボブ．」
　　ボブ「IUSE=goldなsys-devel/binutilsを見つけたので，chrootもせずにemergeしたんだ．」
ジョニー「へぇ，それはなんともricerらしいじゃないか．」
　　ボブ「だけどさ，続いてemergeしようとしたsys-apps/shadowのeconfがコケるんだ．」
ジョニー「それはまたどうして？」
　　ボブ「僕も変だなと思って，手元の自分のCのプログラムをコンパイルしてみたんだ．」
ジョニー「それで？」
　　ボブ「なんと何もコンパイル出来なくなってたんだよ！」
ジョニー「なんてこった！」
　　ボブ「慌ててUSE=-goldでsys-devel/binutilsをemergeしなおそうとしたんだけど．」
ジョニー「ダメだったと．」
　　ボブ「そうなんだ．」
ジョニー「なるほど．」
　　ボブ「なぁ，ジョニー，どうしたいいと思う？」
ジョニー「そんな時はricerなオレ達の強い味方，tinderbox.dev.gentoo.orgの出番さ．」
　　ボブ「何だいそれは？」
ジョニー「systemでstableなブツやクロスコンパイラのバイナリなんかを提供しているトコさ．」
　　ボブ「へぇ，普段自前でしかコンパイルしないから知らなかったよ．」
ジョニー「で，コイツをPORTAGE_BINHOSTで指定して-gKでemergeすれば良いんじゃないかな？」
　　ボブ「具体的には僕の場合はどうやるんだい？」
ジョニー「君はなぜかppc32だったよね？」
　　ボブ「うん，x86が嫌いだからね．」
ジョニー「ならこうさ！」

PORTAGE_BINHOST=http://tinderbox.dev.gentoo.org/default-linux/powerpc/ppc32 \
    emerge -gK =sys-devel/binutils-2.18-r3

　　ボブ「へぇ，いつもemergeするのとあんまり変わらないね．」
ジョニー「これで少し古いけどsys-devel/binutilsは治ったハズだよ．」
　　ボブ「なるほど，これで改めてUSE=-goldでsys-devel/binutilsをemergeすれば良いんだね！」
ジョニー「そうさ，簡単だろ？」
　　ボブ「ああ，やっぱりGentooは最高だね！」

Barcamp.Tokyo[2009] = BenTou + Curry;

waitingだったんだけど，「それでも大丈夫だから来い」みたいなことを言われたのでBarcamp Tokyo 2009に行ってきた．
TLUG並に外国人参加率が高くて，そこら中でネイティブっぽい人達の英語が炸裂してて，俺もPowerBoook弄ってまともに話を聞いていない事も相俟って当社比2倍で訳分からんかった．

あるbrainstormingで「barcampの日本人参加率を上げようぜ」みたいなネタが出て，ありえないぐらいマシンガンかましている人がいたが，正直何を言いたいのかさっぱり聞き取れんかった．
これは新手のプレイだね，間違い無い．

つーか，良く考えたら何で日本人参加率を上げたいんだろう？
彼らが都合の良い英語をプロトコルに使って，実のある話が出来れば日本人参加率が低くても良さそうなもんだけどなぁ．
仮に日本語でのプレゼンやら質疑応答を許可したとしても，そこら中でマシンガンかましているのが大多数だったら，普段英語なんか使う機会が殆ど無い日本人の参加率が上がる訳無ぇだろ，とかここではdisってみる．
少なくとも俺には「郷には入れば郷に従え」ってのが強迫観念みたいに頭から離れんよ．

言い訳しておくと，俺はコードのコメントは悉く英語だし，情報が英語で書かれていても知りたい情報なら読むし，IRCで1337 speakでフザケてたりするけど，耳と口は英語化してないんだよなぁ．
大抵の日本人はコードのコメントは日本語だし，情報が英語で書かれていたら読むのを躊躇うし，IRCで1337 speakなんかしないので，もっと英語化はしていないと思うんよ．

だから，向こうがマシンガンを捨ててカタナに装備を変えるか，こっちがカタナを捨ててマシンガンを装備するかのどちらかをしないと同じ戦場でまともに戦えない．
で，不味い事にマシンガンの方が戦力的に見て圧倒的に有利と言う現状がある訳で，極一部のサムライはカタナを捨ててマシンガンを装備するけど，残りの人達はカタナを持ったまま突撃するか，出島を作って鎖国するか，カタナを捨てて畑を耕してる．

brainstormingは基本的に否定/批判を排したブツだから，その場でどうこうってのはやらなかったし，する気も無かったけど，あそこでマシンガンぶっ放してた人達は最初からマシンガンだけしか装備していなかったとか，ただ単にカタナで斬り合った経験が無いだけだったりしねぇ？
それを一方的に「fair playじゃねぇ！！1」とか言う気は無いし，俺はカタナが結構好きだから別に構わないけど，同じ戦場でまともに戦う事を一番に望んでいるなら，マシンガンをぶっ放してた方はカタナも装備してみようとか，カタナでしか斬り合いした事が無いならマシンガンでもぶっ放してみようとか，っつー言う気概くらいはあっても良いと思うんだよね．

そう言う意味では拙い日本語でコミュニケーションをしようとしてくれるガイジンさんにはとても感謝したいし，俺のbr0ken Englishでも良いなら受け答えしてあげたいと思う．
ま，中々巧く話が進まない所もあってもどかしいけど，だがそれが良い． :)

ああ，そうそう．昼飯の弁当と夕食のカレーはタダ飯だったのでこんなタイトルになってます．深い意味はありません． :DDD

wm.lineage->next();

graphvizがタルくなったので，inkscapeを乗り換えた．
んで，色着けて線が交わらない様にしてみた． :)
SVGはここに晒しておこう．
[using inkscape instead of graphviz, then colorize and flatten. :)
want SVG? here it is.]

線はそれなりに関連があるって事で，必ずしもforkやrewriteを意味する分けでは無かったりする．
タイル型WMでないモノも入っていたり，そもそもWMじゃないモノも入っているがそれなりに意味がある．
[lines just indicate their relation, not only fork/rewrite.
There is some non-tiling WMs, more over few ones are not WM.
But they're worth to mention for explaining about recent GUI improvement for experienced users.]

あとはmultitalkの資料が間に合うかどうかだな． :p
[hmm, making presentation 2D map by multitalk? oh well. :P]

TLUG.NomiKai++; synthSound(&hardware);

TLUGに行ってきた．
BarCamp-Tokyo2009の中の人がHypertextについて話してたのと，XMLとSQLの香りがするsemantic webの話だった．
皆さんはレイヤが高いですな，あいかわらず． :)
飲み会/二次会ではshojiさんのSunオフレコ話とかJARIさん（北欧のイケメン）のアレとか色々．

帰ってからmatsuuさんのBarCamp-Tokyo2009用の下ごしらえっぽいモノとして，それっぽいgraphvizな絵をでっち上げた．
多分，もうちっと弄る．


上の絵をでっち上げていたら，#vhdlでhardware sound synthesize野郎が現れていた． :DDD

05/10 03:54:30 mad
    I'm planning on making sound generation stuff
05/10 03:56:23 mad
    most of that stuff is based around a phase register being incremented
    by the frequency on each sound cycle (which is pretty low rate -
    typically around 44khz)
05/10 04:02:43 bpadalino
    sounds like a cordic should help you out
05/10 04:04:46 hiyuh
    cordic is not for making sound, imho.
05/10 04:09:48 hiyuh
    that sounds like singletone, variable freq in narrow range, and
    presicion is not so important.
05/10 04:10:38 hiyuh
    maybe, making rom-based nco is enough to do.
05/10 04:14:39 bpadalino
    i don't know if a saw wave would sound very good, but as a phase
    accumulator - a cordic sounds like it would work well
05/10 04:30:24 hiyuh
    I meant cordic is expensive for that use.
05/10 04:30:29 hiyuh
    and saw wave + filter for singletone is not a possibility, anyway.
05/10 04:32:34 hiyuh
    phase accum -> sin or cos rom in appropriate precision -> singletone,
    it's simple rom-based nco.
05/10 04:40:47 bpadalino
    you really think a cordic is that expensive ?
05/10 04:51:49 hiyuh
    bpadalino: yes
05/10 04:51:58 bpadalino
    interesting
05/10 04:55:54 bpadalino
    hiyuh, so if you wanted to create 20 tones, how would you go about
    doing that ?
05/10 04:57:07 hiyuh
    20 tones in same time?
05/10 04:57:31 bpadalino
    yeah
05/10 04:59:05 hiyuh
    these tones are elaborate-time fixed or run-time fixed?
05/10 05:00:05 hiyuh
    I meant these tones are fixed before logic synthesize, or not.
05/10 05:00:29 bpadalino
    runtime fixed tones .. frequency fixed before synthesis, but phase
    programmable ..
05/10 05:00:44 bpadalino
    and i want the sum of the 20 tones on the output
05/10 05:07:54 hiyuh
    you mean "amplitude * (sin(2*pi*f1*t + theta1(t)) + ... sin(2*pi*f20*t
    + theta20(t)))"?
05/10 05:09:10 bpadalino
    yeah
05/10 05:10:53 hiyuh
    if I were you, I'd like to make semi-fixed digital filter or just
    do IFFT.
05/10 05:12:42 bpadalino
    that's what i had figured before, but i was just curious what someone
    else might have thought
05/10 05:13:00 hiyuh
    heh
05/10 05:14:18 bpadalino
    i would like to do my own generic systolic FFT sometime ... i think
    that might be fun
05/10 05:16:23 mad
    the tones parameters are written to at performance time
05/10 05:18:05 mad
    It's for music generation, so the applicable freqs are about 20hz to
    20khz (although tones over something like 4khz aren't particularly
    musical)
05/10 05:19:17 anonissimus
    mad: but as harmonics they are
05/10 05:19:33 mad
    Precision has to be at least 1%, esp. in the "most common range"
    (around 50hz ~ 1000hz)
05/10 05:19:50 mad
    anonissimus: yeah, but those are generated from another process
05/10 05:21:16 anonissimus
    ah
05/10 05:21:38 anonissimus
    know more on music than on generting it with hardware :)
05/10 05:21:57 mad
    My plan is: start with pure phase accumulator, then twist the phase
    around in a couple of functions (incl. one that uses multiplication),
    then use sine wave/funky waveform LUT, apply volume and panning,
    sum the channels together, DAC
05/10 05:24:12 mad
    Uses about 140 bits of registers per channel
05/10 05:27:44 mad
    A real practical design would actually be sample based instead
    (with samples in RAM)
05/10 05:29:23 hiyuh
    you know, your plan violates my assumption that described in the
    above expr.
05/10 05:29:25 hiyuh
    so what I was saying is not good way for you.
05/10 05:29:59 mad
    mm, right
05/10 05:31:35 mad
    sound synthesis isn't so hard because the sampling rate is low
    anyways... and you can do it well in software if you have enough CPU
05/10 05:32:14 hiyuh
    yeah, that's why soft synth is popular atm.
05/10 05:32:40 mad
    no kidding, since it pretty much solves it

つまり，敢えてsoftware sound synthesizeしないっつーことですか？
そいつは物好きだなぁ． :)

MeasureSLOC(&AL9); /* 2009/04 */

AでLで9なdiffstat，4月分．
[diffstat for AL9, for 2009/04.]

 a/bench/BENCH_NARROWER.vhd      |  148 -------
 a/vhdl/CPUMP.vhd                |  275 --------------
 a/vhdl/NARROWER.vhd             |  418 ----------------------
 a/vhdl/WIDER.vhd                |  350 ------------------
 b/bench/BENCH_HS_BUS.vhd        |  105 +++++
 b/bench/BENCH_SB.vhd            |  218 +++++++++++
 b/bench/BENCH_UDACCUM.vhd       |  100 +++++
 b/vhdl/HS_BUS.vhd               |  328 +++++++++++++++++
 b/vhdl/SB_MASTER.vhd            |  629 +++++++++++++++++++++++++++++++++
 b/vhdl/SB_SLAVE.vhd             |  339 ++++++++++++++++++
 b/vhdl/TX_SRC_MUX.vhd           |  180 +++++++++
 b/vhdl/TX_SX_FEBE.vhd           |  338 ++++++++++++++++++
 b/vhdl/UDACCUM.vhd              |  219 +++++++++++
 bench/BENCH_BCMUX.vhd           |    7 
 bench/BENCH_BER_IF_REG.vhd      |   92 ++--
 bench/BENCH_LDPCDDB.vhd         |  471 +++++++++++++++----------
 bench/BENCH_LDPCEDB.vhd         |  398 ++++++---------------
 bench/BENCH_PE2RST.vhd          |   49 +-
 bench/BENCH_TX_SMAP.vhd         |   43 +-
 bench/METABENCH_LDPCDDB.vhd     |  161 ++------
 bench/METABENCH_LDPCEDB.vhd     |  140 ++-----
 bench/METAMETABENCH_LDPCDDB.vhd |  104 +++++
 bench/METAMETABENCH_LDPCEDB.vhd |    4 
 stim/STIM_PN_DATA.vhd           |  156 +++++++-
 stim/STIM_RX_DATA_CARR.vhd      |  139 ++++++-
 stim/STIM_TX_DATA_CARR.vhd      |  135 ++++++-
 vhdl/AFIFO.vhd                  |   30 +
 vhdl/BER_IF_REG.vhd             |  743 ++++++++++++++++++++--------------------
 vhdl/CLDPCDOP.vhd               |   11 
 vhdl/COMMON_TYPE_PKG.vhd        |    7 
 vhdl/DFE_NEGOTIATE.vhd          |  282 ++++++++++-----
 vhdl/ELDPCDII.vhd               |   21 -
 vhdl/FCOD.vhd                   |   24 -
 vhdl/HD2BO.vhd                  |  123 +++---
 vhdl/LDPCD.vhd                  |   35 -
 vhdl/LDPCE.vhd                  |   41 +-
 vhdl/LDPCEDB.vhd                |   30 +
 vhdl/LLR2SC.vhd                 |   57 ++-
 vhdl/PE2RST.vhd                 |  310 +++++++++++-----
 vhdl/PN_BLOB.vhd                |   89 +---
 vhdl/PN_NEGOTIATE.vhd           |  274 ++++++++++----
 vhdl/PSQUASH.vhd                |   72 ++-
 vhdl/S2BER_IF.vhd               |   66 +--
 vhdl/SB2SSB.vhd                 |   83 +++-
 vhdl/SBSSBDD.vhd                |    8 
 vhdl/SFIFO.vhd                  |   16 
 vhdl/VTQUEUE.vhd                |    4 
 47 files changed, 4939 insertions(+), 2933 deletions(-)

やっぱ，10kSLOC逝ってないYO!!1 :DDD
[ZOMG, under 10kSLOC AGAIN!!1 :DDD]

VHDL -= function; VHDL -= procedure;

#vhdlにて，functionもprocedureもいらねぇだろうと寝言を言う野郎が出現．
[At #vhdl, t3h guy shoutz "no function and no procedure FTW!!1". So I'd have to say WTF.]

04/30 20:42:47 algoboy
    i need to create a load register, that load the value on a load
    signal, should the register be combinational or clocked? It has to
    hold the loaded values on the output until new values are loaded.
04/30 22:31:38 hw__
    I've been told that everywhere I call a function, the function is
    replaced by logic. So when I call 5 times a function I've 5 times
    the same logic in my FPGA. How about procedures? Does it depend on
    the class of formal/actual parameter?
04/30 23:51:23 algoboy
    hw__ : it depends on where you are calling the functions. If you
    write code that describes a circuit to do 5xtimes your function in
    one clock cycle then it will generate 5 times the hardware. But if
    you instead create a FSM and call the same function from 5 different
    states it should be synthesized to 1 function hardware, depending
    on if the synthesizing tool can schedule the operation and reuse
    the same hardware.
04/30 23:54:05 algoboy
    also the difference between a procedure and a function is that
    functions have a return value, procedures don't.
04/30 23:55:30 hw__
    algoboy: procedures can have "results" as well: If you use "inout"
    or "out" for parameter mode
04/30 23:57:38 algoboy
    yes, but i was just telling the difference between a procedure and
    function. a procedure doesn't return a value. The same as a void
    function in c/c++.
04/30 23:57:57 hiyuh
    no
04/30 23:58:47 algoboy
    no???
05/01 00:03:42 hiyuh
    procedure is procedure. function is function. not less, not more.
05/01 00:03:50 hiyuh
    if you really want to know what they are, read VHDL LRM or general
    CS book like MIT SICP.
05/01 00:08:56 algoboy
    yes a procedure is a procedure and a function is a function. I was
    just telling the difference between them. You can always transform
    a procedure to a function and a function to a procedure.
05/01 00:10:58 algoboy
    I don't see any benefit of using procedures and functions in VHDL. If
    you wan to create a "function" in VHDL create a circuit instead,
    sequential or combinational. This is a much better approach.
05/01 00:12:29 hiyuh
    whut?
05/01 00:13:14 hiyuh
    then, haven't you ever read the two-process method paper?
05/01 00:14:58 NULL[0]
    algoboy: are you a troll ?
05/01 00:15:47 hiyuh
    NULL[0]: i dont think so. :)
05/01 00:16:47 NULL[0]
    hiyuh: if you read his question, and the comments he made, I would
    not be surprised
05/01 00:17:16 longcat
    meh
05/01 00:18:28 algoboy
    hiyuh: Gaisler's two process method?? What does that have to do with
    procedures and functions.
05/01 00:19:00 hiyuh
    algoboy: yup.
05/01 00:19:33 algoboy
    yes i have, i uses the two process method almost all the time. But
    i never use functions and procedures. So i don't get your question.
05/01 00:20:49 hiyuh
    well, are you codin' vhdl as daily job, or?
05/01 00:21:18 algoboy
    no
05/01 00:21:53 algoboy
    i'm still a student
05/01 00:23:53 hiyuh
    okay, I got it, you should code more to realize why function/procedure
    are.
05/01 00:23:58 hiyuh
    I'm always codin' vhdl as daily job. no function/procedure is
    nightmare for me.
05/01 00:26:15 algoboy
    The only benefit i could think of is if you create your own library
    so that you can reuse.
05/01 00:31:21 hiyuh
    what you're saying looks like "always code by using machine language
    in HEX editor" to me.
05/01 00:31:27 hiyuh
    or, sounds like "paste same code from existing ones, b/c I don't
    like any abstraction."
05/01 00:33:04 drichards
    isn't abstraction the whole point of an HDL?
05/01 00:33:37 MatthiasM
    I use functions for simple things - like counting leading zeros etc
05/01 00:34:06 algoboy
    VHDL is not a programming language so i wouldn't write any machine
    code. I use VHDL to describe hardware and and prefer to work on the
    RTL level.
05/01 00:34:27 MatthiasM
    or procedures for updating more complex counters like this: lsb <=
    (lsb + inc) mod X; msb <= msb + (lsb + inc) / X;
05/01 00:35:06 *
    hiyuh lolz @ "VHDL is not a programming language"
05/01 00:35:15 MatthiasM
    functions are much more flexible as you can decide where to store
    the return value when you call it (or use it directly in an IF)
05/01 00:35:51 algoboy
    hiyuh: :/
05/01 00:35:59 MatthiasM
    procedures can have more then one return value - but you must decide
    if the values are passed/returned as signal or variable
05/01 00:36:43 MatthiasM
    all functions and procedures are basicly combinatorical logic -
    if you need something with a clock - write a new entity
05/01 00:37:22 algoboy
    MatthiasM: so why not write combinatorial logic all the time?
05/01 00:37:35 MatthiasM
    algoboy: LOL
05/01 00:37:50 algoboy
    MatthiasM: instead of a function or procedure
05/01 00:38:29 MatthiasM
    the example of the procedure above - is about ~10 lines of code -
    I need it in 4 places - calling it takes 1 line of code
05/01 00:38:45 MatthiasM
    and it even works when the bit width of the busses are different
    for each call
05/01 00:39:42 drichards
    which is why I like subprogs
05/01 00:39:55 algoboy
    MatthiasM: create the same procedure as a circuit. Use generate to
    generate x instances and also use genric.
05/01 00:39:55 drichards
    they can react to the act bus width, register width, etc.
05/01 00:39:58 algoboy
    the same thing
05/01 00:40:57 MatthiasM
    algoboy: I can call a function/procedure inside a clocked process
    and inside nested control edges - this makes it very easy to write
    complex logic with sequential source code
05/01 00:41:34 MatthiasM
    as a designer I want to write code that is A) easy to write B)
    easy to read C) easy to change
05/01 00:41:56 MatthiasM
    and it's the tools job to create an efficient logic implementation
    based on my source code
05/01 00:43:10 MatthiasM
    ofcourse you have to be careful to not create to wide logic functions
    - which can easily happen if you nest IFs - or check the result of
    combinatorical functions (like "IF x+1 == y THEN .... END IF;")
05/01 00:43:43 MatthiasM
    algoboy: if you understand these - then you can create a complex
    design in a short time
05/01 00:43:51 algoboy
    MatthiasM: i prefere to write synthesizable code, targeting low power,
    low area. Using higher abstraction you rely much on the synthesizing
    tool to do the job for you.
05/01 00:44:10 NULL[0]
    ...
05/01 00:44:32 MatthiasM
    yep - that's why I use Quartus - it's synthesizer is very good -
    it's very hard to create more efficient logic by hand
05/01 00:45:54 algoboy
    oh, fpga synthesizing is one thing, but i am running asic flow and
    it is a huge difference.
05/01 00:46:19 tzanger
    MatthiasM: quartus is for atmel, right?
05/01 00:46:27 MatthiasM
    Altera
05/01 00:46:30 algoboy
    yes
05/01 00:46:35 algoboy
    altera
05/01 00:47:32 tzanger
    er altera
05/01 00:47:33 tzanger
    duh
05/01 00:47:41 tzanger
    I knew it was an A. :-)
05/01 00:47:47 algoboy
    :p
05/01 00:47:49 *
    hiyuh petz NULL[0]. :)
05/01 00:48:09 MatthiasM
    algoboy: take a look at some old code: http://pastebin.com/d418ebc0e
05/01 00:49:10 MatthiasM
    the production code uses constants instead of hard coded values
    ofcourse
05/01 00:52:14 algoboy
    MatthiasM: VGA controller?
05/01 00:52:25 MatthiasM
    sync generator for DVI
05/01 00:52:34 MatthiasM
    (VGA doesn't use DE signal)
05/01 00:52:52 algoboy
    oh :)
05/01 00:53:17 MatthiasM
    but it started as VGA generator - that's why the clock is called
    vga_clk
05/01 00:53:41 hiyuh
    rename FTW!!1 :)
05/01 00:54:15 MatthiasM
    algoboy: see the splitted counter in line 28 and the compare in line
    35 ? the current code uses procedures for increment and a function
    for compare
05/01 00:54:20 algoboy
    MatthiasM: that is nice code :) no functions or procedures :)
05/01 00:54:45 MatthiasM
    that way I can just write "IF compare(row_cnt2, row_cnt1, 12, 805)
    then .... end if;"
05/01 00:56:28 MatthiasM
    algoboy: eg http://pastebin.com/d7c8c5b34
05/01 00:56:41 MatthiasM
    much more readable
05/01 00:57:52 algoboy
    yes it is, if you know what the functions does.
05/01 00:58:18 MatthiasM
    that's why you can put comments into the VHDL files
05/01 01:00:08 algoboy
    :p
05/01 01:00:24 *
    hiyuh sticks more popcorn to the microwave.
05/01 01:00:40 *
    MatthiasM steals hiyuh's popcorn
05/01 01:01:00 hiyuh
    lol
05/01 01:01:16 MatthiasM
    :DD

ポップコーンを喰えたので良しとする． :DDD
[PLESIOUS POPCORN TIME, YUM!!1 :DDD]

updateCRC(&CRC, &byte);

ちとCRCをムニャる必要が出て来たので，例の本をゴニョると，byte streamに対して計算するアルゴリズムが載っていたので，2時間くらいモニョモニョしてVHDLで実装した．

先ず，popularな生成多項式をWikipediaからパクってきてpackageに．

library ieee;
use ieee.std_logic_1164.all;

package CRC_GENERATOR_PKG is

 constant cCRC_1_GENERATOR              : std_logic_vector;
 constant cCRC_4_ITU_GENERATOR          : std_logic_vector;
 constant cCRC_5_ITU_GENERATOR          : std_logic_vector;
 constant cCRC_5_USB_GENERATOR          : std_logic_vector;
 constant cCRC_6_ITU_GENERATOR          : std_logic_vector;
 constant cCRC_7_GENERATOR              : std_logic_vector;
 constant cCRC_8_ATM_GENERATOR          : std_logic_vector;
 constant cCRC_8_CCITT_GENERATOR        : std_logic_vector;
 constant cCRC_8_Dallas_Maxim_GENERATOR : std_logic_vector;
 constant cCRC_8_GENERATOR              : std_logic_vector;
 constant cCRC_8_SAE_J1850_GENERATOR    : std_logic_vector;
 constant cCRC_10_GENERATOR             : std_logic_vector;
 constant cCRC_11_GENERATOR             : std_logic_vector;
 constant cCRC_12_GENERATOR             : std_logic_vector;
 constant cCRC_15_CAN_GENERATOR         : std_logic_vector;
 constant cCRC_16_CCITT_GENERATOR       : std_logic_vector;
 constant cCRC_16_DNP_GENERATOR         : std_logic_vector;
 constant cCRC_16_IBM_GENERATOR         : std_logic_vector;
 constant cCRC_24_Radix_64_GENERATOR    : std_logic_vector;
 constant cCRC_30_GENERATOR             : std_logic_vector;
 constant cCRC_32_IEEE_802_3_GENERATOR  : std_logic_vector;
 constant cCRC_32_Castagnoli_GENERATOR  : std_logic_vector;
 constant cCRC_32_Koopman_GENERATOR     : std_logic_vector;
 constant cCRC_64_ISO_3309_GENERATOR    : std_logic_vector;
 constant cCRC_64_ECMA_182_GENERATOR    : std_logic_vector;

end package CRC_GENERATOR_PKG;

package body CRC_GENERATOR_PKG is

 type tCRC_TYPE is (
  CRC_1,
  CRC_4_ITU,
  CRC_5_ITU,
  CRC_5_USB,
  CRC_6_ITU,
  CRC_7,
  CRC_8_ATM,
  CRC_8_CCITT,
  CRC_8_Dallas_Maxim,
  CRC_8,
  CRC_8_SAE_J1850,
  CRC_10,
  CRC_11,
  CRC_12,
  CRC_15_CAN,
  CRC_16_CCITT,
  CRC_16_DNP,
  CRC_16_IBM,
  CRC_24_Radix_64,
  CRC_30,
  CRC_32_IEEE_802_3,
  CRC_32_Castagnoli,
  CRC_32_Koopman,
  CRC_64_ISO_3309,
  CRC_64_ECMA_182
 );

 type tCRC_LENGTH is array (tCRC_TYPE) of integer range 1 to 64;
 constant cCRC_LENGTH : tCRC_LENGTH := (
  CRC_1              =>  1,
  CRC_4_ITU          =>  4,
  CRC_5_ITU          =>  5,
  CRC_5_USB          =>  5,
  CRC_6_ITU          =>  6,
  CRC_7              =>  7,
  CRC_8_ATM          =>  8,
  CRC_8_CCITT        =>  8,
  CRC_8_Dallas_Maxim =>  8,
  CRC_8              =>  8,
  CRC_8_SAE_J1850    =>  8,
  CRC_10             => 10,
  CRC_11             => 11,
  CRC_12             => 12,
  CRC_15_CAN         => 15,
  CRC_16_CCITT       => 16,
  CRC_16_DNP         => 16,
  CRC_16_IBM         => 16,
  CRC_24_Radix_64    => 24,
  CRC_30             => 30,
  CRC_32_IEEE_802_3  => 32,
  CRC_32_Castagnoli  => 32,
  CRC_32_Koopman     => 32,
  CRC_64_ISO_3309    => 64,
  CRC_64_ECMA_182    => 64
 );

 type tCRC_GENERATOR is array (tCRC_TYPE) of std_logic_vector(64 downto 0);
 constant cCRC_GENERATOR : tCRC_GENERATOR := (
  CRC_1              =>
   -- x^1  + x^0
   (64 downto  1+1 => '0') & "11",
  CRC_4_ITU          =>
   -- x^4  + x^1  + x^0
   (64 downto  4+1 => '0') & "10011",
  CRC_5_ITU          =>
   -- x^5  + x^4  + x^2  + x^0
   (64 downto  5+1 => '0') & "110101",
  CRC_5_USB          =>
   -- x^5  + x^2  + x^0
   (64 downto  5+1 => '0') & "100101",
  CRC_6_ITU          =>
   -- x^6  + x^1  + x^0
   (64 downto  6+1 => '0') & "1000011",
  CRC_7              =>
   -- x^7  + x^3  + x^0
   (64 downto  7+1 => '0') & "10001001",
  CRC_8_ATM          =>
   -- x^8  + x^2  + x^1  + x^0
   (64 downto  8+1 => '0') & "100000111",
  CRC_8_CCITT        =>
   -- x^8  + x^7  + x^3  + x^2  + x^0
   (64 downto  8+1 => '0') & "110001101",
  CRC_8_Dallas_Maxim =>
   -- x^8  + x^5  + x^4  + x^0
   (64 downto  8+1 => '0') & "100110001",
  CRC_8              =>
   -- x^8  + x^7  + x^6  + x^4  + x^2  + x^0
   (64 downto  8+1 => '0') & "111010101",
  CRC_8_SAE_J1850    =>
   -- x^8  + x^4  + x^3  + x^2  + x^0
   (64 downto  8+1 => '0') & "100011101",
  CRC_10             =>
   -- x^10 + x^9  + x^5  + x^4  + x^1  + x^0
   (64 downto 10+1 => '0') & "11000110011",
  CRC_11             =>
   -- x^11 + x^9  + x^8  + x^7  + x^2  + x^0
   (64 downto 11+1 => '0') & "101110000101",
  CRC_12             =>
   -- x^12 + x^11 + x^3  + x^2  + x^1  + x^0
   (64 downto 12+1 => '0') & "1100000001111",
  CRC_15_CAN         =>
   -- x^15 + x^14 + x^10 + x^8  + x^7  + x^4  + x^3  + x^0
   (64 downto 15+1 => '0') & "1100010110011001",
  CRC_16_CCITT       =>
   -- x^16 + x^12 + x^5  + x^0
   (64 downto 16+1 => '0') & "10001000000100001",
  CRC_16_DNP         =>
   -- x^16 + x^13 + x^12 + x^11 + x^10 + x^8  + x^6  + x^5  + x^2  + x^0
   (64 downto 16+1 => '0') & "10011110101100101",
  CRC_16_IBM         =>
   -- x^16 + x^15 + x^2  + x^0
   (64 downto 16+1 => '0') & "11000000000000101",
  CRC_24_Radix_64    =>
   -- x^24 + x^23 + x^18 + x^17 + x^14 + x^11 + x^10 + x^7  + x^6  + x^5
   --      + x^4  + x^3  + x^1  + x^0
   (64 downto 24+1 => '0') & "1100001100100110011111011",
  CRC_30             =>
   -- x^30 + x^29 + x^21 + x^20 + x^15 + x^13 + x^12 + x^11 + x^8  + x^7
   --      + x^6  + x^2  + x^1  + x^0
   (64 downto 30+1 => '0') & "1100000001100001011100111000111",
  CRC_32_IEEE_802_3  =>
   -- x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8  + x^7
   --      + x^5  + x^4  + x^2  + x^1  + x^0
   (64 downto 32+1 => '0') & "100000100110000010001110110110111",
  CRC_32_Castagnoli  =>
   -- x^32 + x^28 + x^27 + x^26 + x^25 + x^23 + x^22 + x^20 + x^19 + x^18
   --      + x^14 + x^13 + x^11 + x^10 + x^9  + x^8  + x^6  + x^0
   (64 downto 32+1 => '0') & "100011110110111000110111101000001",
  CRC_32_Koopman     =>
   -- x^32 + x^30 + x^29 + x^28 + x^26 + x^20 + x^19 + x^17 + x^16 + x^15
   --      + x^11 + x^10 + x^7  + x^6  + x^4  + x^2  + x^1  + x^0
   (64 downto 32+1 => '0') & "101110100000110111000110011010111",
  CRC_64_ISO_3309    =>
   -- x^64 + x^4  + x^3  + x^1  + x^0
   "10000000000000000000000000000000000000000000000000000000000011011",
  CRC_64_ECMA_182    =>
   -- x^64 + x^62 + x^57 + x^55 + x^54 + x^53 + x^52 + x^47 + x^46 + x^45
   --      + x^40 + x^39 + x^38 + x^37 + x^35 + x^33 + x^32 + x^31 + x^29
   --      + x^27 + x^24 + x^23 + x^22 + x^21 + x^19 + x^17 + x^13 + x^12
   --      + x^10 + x^9  + x^7  + x^4  + x^1  + x^0
   "10100001011110000111000011110101110101001111010100011011010010011"
 );

 constant cCRC_1_GENERATOR              : std_logic_vector := cCRC_GENERATOR(CRC_1             )(cCRC_LENGTH(CRC_1             ) downto 0);
 constant cCRC_4_ITU_GENERATOR          : std_logic_vector := cCRC_GENERATOR(CRC_4_ITU         )(cCRC_LENGTH(CRC_4_ITU         ) downto 0);
 constant cCRC_5_ITU_GENERATOR          : std_logic_vector := cCRC_GENERATOR(CRC_5_ITU         )(cCRC_LENGTH(CRC_5_ITU         ) downto 0);
 constant cCRC_5_USB_GENERATOR          : std_logic_vector := cCRC_GENERATOR(CRC_5_USB         )(cCRC_LENGTH(CRC_5_USB         ) downto 0);
 constant cCRC_6_ITU_GENERATOR          : std_logic_vector := cCRC_GENERATOR(CRC_6_ITU         )(cCRC_LENGTH(CRC_6_ITU         ) downto 0);
 constant cCRC_7_GENERATOR              : std_logic_vector := cCRC_GENERATOR(CRC_7             )(cCRC_LENGTH(CRC_7             ) downto 0);
 constant cCRC_8_ATM_GENERATOR          : std_logic_vector := cCRC_GENERATOR(CRC_8_ATM         )(cCRC_LENGTH(CRC_8_ATM         ) downto 0);
 constant cCRC_8_CCITT_GENERATOR        : std_logic_vector := cCRC_GENERATOR(CRC_8_CCITT       )(cCRC_LENGTH(CRC_8_CCITT       ) downto 0);
 constant cCRC_8_Dallas_Maxim_GENERATOR : std_logic_vector := cCRC_GENERATOR(CRC_8_Dallas_Maxim)(cCRC_LENGTH(CRC_8_Dallas_Maxim) downto 0);
 constant cCRC_8_GENERATOR              : std_logic_vector := cCRC_GENERATOR(CRC_8             )(cCRC_LENGTH(CRC_8             ) downto 0);
 constant cCRC_8_SAE_J1850_GENERATOR    : std_logic_vector := cCRC_GENERATOR(CRC_8_SAE_J1850   )(cCRC_LENGTH(CRC_8_SAE_J1850   ) downto 0);
 constant cCRC_10_GENERATOR             : std_logic_vector := cCRC_GENERATOR(CRC_10            )(cCRC_LENGTH(CRC_10            ) downto 0);
 constant cCRC_11_GENERATOR             : std_logic_vector := cCRC_GENERATOR(CRC_11            )(cCRC_LENGTH(CRC_11            ) downto 0);
 constant cCRC_12_GENERATOR             : std_logic_vector := cCRC_GENERATOR(CRC_12            )(cCRC_LENGTH(CRC_12            ) downto 0);
 constant cCRC_15_CAN_GENERATOR         : std_logic_vector := cCRC_GENERATOR(CRC_15_CAN        )(cCRC_LENGTH(CRC_15_CAN        ) downto 0);
 constant cCRC_16_CCITT_GENERATOR       : std_logic_vector := cCRC_GENERATOR(CRC_16_CCITT      )(cCRC_LENGTH(CRC_16_CCITT      ) downto 0);
 constant cCRC_16_DNP_GENERATOR         : std_logic_vector := cCRC_GENERATOR(CRC_16_DNP        )(cCRC_LENGTH(CRC_16_DNP        ) downto 0);
 constant cCRC_16_IBM_GENERATOR         : std_logic_vector := cCRC_GENERATOR(CRC_16_IBM        )(cCRC_LENGTH(CRC_16_IBM        ) downto 0);
 constant cCRC_24_Radix_64_GENERATOR    : std_logic_vector := cCRC_GENERATOR(CRC_24_Radix_64   )(cCRC_LENGTH(CRC_24_Radix_64   ) downto 0);
 constant cCRC_30_GENERATOR             : std_logic_vector := cCRC_GENERATOR(CRC_30            )(cCRC_LENGTH(CRC_30            ) downto 0);
 constant cCRC_32_IEEE_802_3_GENERATOR  : std_logic_vector := cCRC_GENERATOR(CRC_32_IEEE_802_3 )(cCRC_LENGTH(CRC_32_IEEE_802_3 ) downto 0);
 constant cCRC_32_Castagnoli_GENERATOR  : std_logic_vector := cCRC_GENERATOR(CRC_32_Castagnoli )(cCRC_LENGTH(CRC_32_Castagnoli ) downto 0);
 constant cCRC_32_Koopman_GENERATOR     : std_logic_vector := cCRC_GENERATOR(CRC_32_Koopman    )(cCRC_LENGTH(CRC_32_Koopman    ) downto 0);
 constant cCRC_64_ISO_3309_GENERATOR    : std_logic_vector := cCRC_GENERATOR(CRC_64_ISO_3309   )(cCRC_LENGTH(CRC_64_ISO_3309   ) downto 0);
 constant cCRC_64_ECMA_182_GENERATOR    : std_logic_vector := cCRC_GENERATOR(CRC_64_ECMA_182   )(cCRC_LENGTH(CRC_64_ECMA_182   ) downto 0);

end package body CRC_GENERATOR_PKG;

次に，生成多項式とbit per byteをgenericで指定して，例のアルゴリズムをそのままtwo-process手法で実装．

library ieee;
use ieee.std_logic_1164.all;
use work.CRC_GENERATOR_PKG.all;

package BYTE_CRC_PKG is

 component BYTE_CRC is
  generic (
   BPB       : integer range 1 to integer'high := 8;
   GENERATOR : std_logic_vector                := cCRC_16_CCITT_GENERATOR;
   ASYNC     : boolean                         := false
  );
  port (
   iCLK : in  std_logic;
   iCLR : in  std_logic;
   iINI : in  std_logic;
   iE   : in  std_logic;
   iD   : in  std_logic_vector(         BPB-1 downto 0);
   oE   : out std_logic;
   oD   : out std_logic_vector(         BPB-1 downto 0);
   oCRC : out std_logic_vector((GENERATOR'length-1)-1 downto 0)
  );
 end component BYTE_CRC;

end package BYTE_CRC_PKG;

package body BYTE_CRC_PKG is

 -- NOTE: This body should keep to be empty to stub.

end package body BYTE_CRC_PKG;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.CRC_GENERATOR_PKG.all;

entity BYTE_CRC is
 generic (
  BPB       : integer range 1 to integer'high := 8;
  GENERATOR : std_logic_vector                := cCRC_16_CCITT_GENERATOR;
  ASYNC     : boolean                         := false
 );
 port (
  iCLK : in  std_logic;
  iCLR : in  std_logic;
  iINI : in  std_logic;
  iE   : in  std_logic;
  iD   : in  std_logic_vector(         BPB-1 downto 0);
  oE   : out std_logic;
  oD   : out std_logic_vector(         BPB-1 downto 0);
  oCRC : out std_logic_vector((GENERATOR'length-1)-1 downto 0)
 );
begin
 A_BPB_CHECK : assert ((GENERATOR'length-1) mod BPB = 0)
  report BYTE_CRC'instance_name &
   "GENERATOR'length-1 should be congrunet to 0 modulo BPB!!1"
   severity error;
end entity BYTE_CRC;

architecture TP of BYTE_CRC is

 pure function fLEAD_BIT_INDEX (
  iX : std_logic_vector
 ) return integer is
 begin
  F_L : for l in iX'range loop
   if (iX(l) = '1') then
    return l;
   end if;
  end loop F_L;
  return -1;
 end function fLEAD_BIT_INDEX;

 type tCRC_REMAINDER is
  array (0 to 2**BPB-1) of
   std_logic_vector((GENERATOR'length-1)-1 downto 0);

 pure function fCRC_REMAINDER (
  iG : std_logic_vector
 ) return tCRC_REMAINDER is
  variable vLG            : integer range -1 to iG'length-1;
  variable vQ             : std_logic_vector(BPB-1 downto 0);
  variable vR             : std_logic_vector(vQ'length+(iG'length-1)-1 downto 0);
  variable vLR            : integer range -1 to vR'length-1;
  variable vG             : std_logic_vector(vR'range);
  variable vCRC_REMAINDER : tCRC_REMAINDER;
 begin
  vLG := fLEAD_BIT_INDEX(iG);
  F_Q : for Q in 0 to 2**vQ'length-1 loop
   vQ  := conv_std_logic_vector(Q, vQ'length);
   vR  := vQ & ((iG'length-1)-1 downto 0 => '0');
   vLR := fLEAD_BIT_INDEX(vR);
   W_R : while (vLR >= vLG) loop
    vG  :=
     (vG'length-1 downto vLR+1 => '0') &
     iG(vLG downto 0)                  &
     (vLR-vLG-1 downto 0 => '0');
    vR  := vR xor vG;
    vLR := fLEAD_BIT_INDEX(vR);
   end loop W_R;
   -- synthesis translate_off
   A_CRC_REMAINDER_CHECK :
    assert (vR(vR'length-1 downto iG'length-1) =
     (vR'length-1 downto iG'length-1 => '0'))
     report fCRC_REMAINDER'instance_name &
      "CRC remainder is out of range!!1"
     severity error;
   -- synthesis translate_on
   vCRC_REMAINDER(Q) := vR((iG'length-1)-1 downto 0);
  end loop F_Q;
  return vCRC_REMAINDER;
 end function fCRC_REMAINDER;

 constant cCRC_REMAINDER : tCRC_REMAINDER := fCRC_REMAINDER(GENERATOR);

 type tCRC is
  array (((GENERATOR'length-1)/BPB)-1 downto 0) of
   std_logic_vector(BPB-1 downto 0);

 type t is record
  E   : std_logic;
  D   : std_logic_vector(BPB-1 downto 0);
  RI  : std_logic_vector(BPB-1 downto 0);
  CRC : tCRC;
 end record t;

 constant c : t := (
  E   => '0',
  D   => (BPB-1 downto 0 => '0'),
  RI  => (BPB-1 downto 0 => '0'),
  CRC => (tCRC'range => (BPB-1 downto 0 => '0'))
 );

 signal g : t;
 signal r : t := c;

begin

 P_COMB : process (iINI, iE, iD, r)
  variable v : t := c;
 begin
  if (iINI = '1') then
   v.E  := '0';
   v.D  := (BPB-1 downto 0 => '0');
   v.RI := (BPB-1 downto 0 => '0');
   F_CRC_INITIALIZE : for i in tCRC'range loop
    v.CRC(i) := (BPB-1 downto 0 => '0');
   end loop F_CRC_INITIALIZE;
  elsif (iE = '1') then
   v.E  := '1';
   v.D  := iD;
   v.RI := iD xor r.CRC(tCRC'high);
   F_CRC_UPDATE : for i in tCRC'range loop
    if (i = tCRC'low) then
     v.CRC(i) :=
      cCRC_REMAINDER(conv_integer(unsigned(v.RI)))((i+1)*BPB-1 downto i*BPB);
    else
     v.CRC(i) :=
      r.CRC(i-1) xor
      cCRC_REMAINDER(conv_integer(unsigned(v.RI)))((i+1)*BPB-1 downto i*BPB);
    end if;
   end loop F_CRC_UPDATE;
  else
   v.E   := '0';
   v.D   := r.D;
   v.RI  := r.RI;
   v.CRC := r.CRC;
  end if;

  g  <= v;
  oE <= r.E;
  oD <= r.D;
  F_CRC_OUTPUT : for i in tCRC'range loop
   oCRC((i+1)*BPB-1 downto i*BPB) <= r.CRC(i);
  end loop F_CRC_OUTPUT;
 end process P_COMB;

 G_ASYNC : if (ASYNC = true) generate
 begin
  P_SEQ : process (iCLR, iCLK)
  begin
   if (iCLR = '1') then
    r <= c;
   elsif (iCLK'event and iCLK = '1') then
    r <= g;
   end if;
  end process P_SEQ;
 end generate G_ASYNC;

 G_SYNC : if (ASYNC = false) generate
 begin
  P_SEQ : process (iCLK)
  begin
   if (iCLK'event and iCLK = '1') then
    if (iCLR = '1') then
     r <= c;
    else
     r <= g;
    end if;
   end if;
  end process P_SEQ;
 end generate G_SYNC;

end architecture TP;

最後に，やる気の無いテストベンチをでっち上げ．

library ieee;
use ieee.std_logic_1164.all;
use work.CRC_GENERATOR_PKG.all;
use work.BYTE_CRC_PKG.all;

entity BENCH_BYTE_CRC is
begin
end entity BENCH_BYTE_CRC;

architecture BENCH of BENCH_BYTE_CRC is

 constant cCLK_CYCLE : time := 1 us;
 constant cCLR_TIME  : time := 10*cCLK_CYCLE;

 signal sCLK  : std_logic := '0';
 signal sCLR  : std_logic := '1';

 type tST is (INIT, BYTE1, BYTE0);

 signal sST  : tST       := INIT;
 signal sINI : std_logic := '0';
 signal sE   : std_logic := '0';
 signal sD   : std_logic_vector(7 downto 0) := (7 downto 0 => '0');

 signal sBYTE_CRC_oE   : std_logic;
 signal sBYTE_CRC_oD   : std_logic_vector( 7 downto 0);
 signal sBYTE_CRC_oCRC : std_logic_vector(15 downto 0);

begin

 P_sCLK : process
 begin
  sCLK <= '0'; wait for cCLK_CYCLE/2;
  sCLK <= '1'; wait for cCLK_CYCLE/2;
 end process P_sCLK;

 P_sCLR : process
 begin
  sCLR <= '1'; wait for cCLR_TIME;
  sCLR <= '0'; wait;
 end process P_sCLR;

 P_sST_sINI_sE_sD : process (sCLK)
 begin
  if (sCLK'event and sCLK = '1') then
   if (sCLR = '1') then
    sST  <= INIT;
    sINI <= '1';
    sE   <= '0';
    sD   <= (7 downto 0 => '0');
   else
    case sST is
     when INIT   =>
      sST  <= BYTE1;
      sINI <= '0';
      sE   <= '1';
      sD   <= X"6D";
     when BYTE1  =>
      sST  <= BYTE0;
      sINI <= '0';
      sE   <= '1';
      sD   <= X"27";
     when BYTE0  =>
      sST  <= BYTE0;
      sINI <= '0';
      sE   <= '0';
      sD   <= sD;
     when others =>
      sST  <= INIT;
      sINI <= '1';
      sE   <= '0';
      sD   <= (7 downto 0 => '0');
    end case;
   end if;
  end if;
 end process P_sST_sINI_sE_sD;

 U_BYTE_CRC : BYTE_CRC
 generic map (
  BPB       => 8,
  GENERATOR => cCRC_16_IBM_GENERATOR,
  ASYNC     => false
 )
 port map (
  iCLK => sCLK,
  iCLR => sCLR,
  iINI => sINI,
  iE   => sE,
  iD   => sD,
  oE   => sBYTE_CRC_oE,
  oD   => sBYTE_CRC_oD,
  oCRC => sBYTE_CRC_oCRC
 );

end architecture BENCH;

pipeline化をサボっているのでクロックが早くなるとダメになる事ウケアイ．
ま，quick'n'dirtyっつー事で． :)

MeasureSLOC(&AL9); /* 2009/03 */

AでLで9なdiffstat，3月分．
[diffstat for AL9, for 2009/03.]

 a/vhdl/BUFGMUX4_COMPAT.vhd    |  182 --------
 a/vhdl/CBUF.vhd               |  298 -------------
 a/vhdl/DCM_TROLL.vhd          |  320 --------------
 a/vhdl/FBUFG.vhd              |   91 ----
 a/vhdl/FBUFGCE.vhd            |   95 ----
 a/vhdl/LDPCD-dummy.vhd        |  116 -----
 a/vhdl/LLR2SCB.vhd            |  187 --------
 b/bench/BENCH_BER_IF_REG.vhd  |  134 ++++++
 b/bench/BENCH_SCB2SCN2SCW.vhd |  208 +++++++++
 b/bench/BENCH_TSR_CLK.vhd     |   63 ++
 b/bench/BENCH_WSX_LFSR.vhd    |  155 +++++++
 b/vhdl/BCBOOL.vhd             |  451 ++++++++++++++++++++
 b/vhdl/BER_IF_REG.vhd         |  682 +++++++++++++++++++++++++++++++
 b/vhdl/COMMON_TYPE_PKG.vhd    |   54 ++
 b/vhdl/CSSSTM.vhd             |  262 ++++++++++++
 b/vhdl/LDPCD-stub.vhd         |  113 +++++
 b/vhdl/LDPCE-stub.vhd         |  183 ++++++++
 b/vhdl/LLR2SC.vhd             |  267 ++++++++++++
 b/vhdl/SCN.vhd                |  237 ++++++++++
 b/vhdl/SCW.vhd                |  242 +++++++++++
 b/vhdl/TEIADD.vhd             |  190 ++++++++
 b/vhdl/TSR_CLK.vhd            |  475 +++++++++++++++++++++
 b/vhdl/WSX_LFSR.vhd           |  408 ++++++++++++++++++
 bench/BENCH_BER_IF_CLK.vhd    |    8 
 bench/BENCH_FCO.vhd           |   61 +-
 vhdl/BCMUX.vhd                |  149 ++++--
 vhdl/BER_IF_CLK.vhd           |    8 
 vhdl/BYTEREV.vhd              |   37 +
 vhdl/CLDPCDOP.vhd             |   83 +--
 vhdl/ELDPCDII.vhd             |   43 -
 vhdl/FCO.vhd                  |  157 ++-----
 vhdl/FCOD.vhd                 |  329 +++++++--------
 vhdl/HD2BO.vhd                |  219 +++++-----
 vhdl/LDPCD.vhd                |   59 +-
 vhdl/LDPCE.vhd                |   79 ---
 vhdl/LDPCEDB.vhd              |  914 +++++++++++++++++-------------------------
 vhdl/NIBBLESW.vhd             |   37 +
 vhdl/PN_NEGOTIATE.vhd         |   14 
 vhdl/S2BER_IF.vhd             |  278 ++++++++----
 vhdl/SBSSBDD.vhd              |  124 ++++-
 vhdl/SCB.vhd                  |  217 ++-------
 vhdl/SELDPCDIIM.vhd           |   16 
 vhdl/VTQUEUE.vhd              |  103 ++--
 43 files changed, 5554 insertions(+), 2794 deletions(-)

10kSLOC逝ってないYO!!1 :DDD
[ZOMG, under 10kSLOC!!1 :DDD]

ファイル名で分かるがLDPC関係なので，勉強ついでにコレを買ってチョロチョロ読んでいる．Reed-Solomon, Turbo, LDPCが一通り載ってるし，分厚くてとても良さ気． :)
[Yup, it's LDPC related project, so I bought this book. It explains Reed-Solomon, Turbo and LDPC. AND THEN ITZ T3H THICK!!1 :)]

Ypsilon.Makefile.karma--;

Ypsilon，R^6RSなscheme，GCがアレでメニィコアによろしいらしい．
Makefileより，

#   Makefile for Linux, FreeBSD, OpenBSD, and Darwin
#   Requirements: GNU Make, GCC 4.0 or later
#   Options: DESTDIR, PREFIX, DATAMODEL(ILP32/LP64), USE_SDL(ON)

PROG   = ypsilon

PREFIX   = /usr/local

CPPFLAGS = -DNDEBUG -DSYSTEM_SHARE_PATH='"$(DESTDIR)$(PREFIX)/share/$(PROG)"'

CXXFLAGS = -pipe -x c++ -O3 -fstrict-aliasing -fomit-frame-pointer -momit-leaf-frame-pointer

SRCS   = file.cpp main.cpp vm0.cpp object_heap_compact.cpp subr_flonum.cpp vm1.cpp object_set.cpp \
    subr_hash.cpp vm2.cpp object_slab.cpp subr_list.cpp interpreter.cpp serialize.cpp \
           vm3.cpp port.cpp subr_others.cpp arith.cpp printer.cpp subr_port.cpp subr_r5rs_arith.cpp \
    equiv.cpp reader.cpp ffi.cpp subr_base.cpp bag.cpp \
           subr_unicode.cpp hash.cpp subr_base_arith.cpp ucs4.cpp ioerror.cpp subr_bitwise.cpp utf8.cpp \
    main.cpp subr_bvector.cpp violation.cpp object_factory.cpp \
           subr_ffi.cpp object_heap.cpp subr_fixnum.cpp bit.cpp list.cpp fasl.cpp socket.cpp subr_socket.cpp

VPATH   = src

UNAME   = $(shell uname -a)

ifndef DATAMODEL
  ifeq ($(shell echo | $(CXX) -E -dM - | grep '__LP64__'), )
    DATAMODEL = ILP32
  else
    DATAMODEL = LP64
  endif
endif

ifneq (, $(findstring Linux, $(UNAME)))
  ifeq ($(shell $(CXX) -dumpspecs | grep 'march=native'), )
    ifeq ($(DATAMODEL), ILP32)  
      CXXFLAGS += -march=i686
    endif
  else
    CXXFLAGS += -march=native
  endif
  ifeq ($(shell grep -i sse2 /proc/cpuinfo), )
    CXXFLAGS += -msse
  else
    CXXFLAGS += -msse2
  endif
  CXXFLAGS += -mfpmath=sse -pthread
  ifeq ($(DATAMODEL), ILP32)  
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=32
    CXXFLAGS += -m32
    LDFLAGS = -m32
    ASFLAGS = --32
    SRCS += ffi_stub_linux.s
  else
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=64
    CXXFLAGS += -m64
    LDFLAGS = -m64
    ASFLAGS = --64
    SRCS += ffi_stub_linux64.s
  endif
  LDLIBS = -lpthread -ldl
endif

ifneq (, $(findstring FreeBSD, $(UNAME)))
  ifeq ($(shell $(CXX) -dumpspecs | grep 'march=native'), )
    ifeq ($(DATAMODEL), ILP32)  
      CXXFLAGS += -march=i686
    endif
  else
    CXXFLAGS += -march=native
  endif
  ifeq ($(shell dmesg | grep -i sse2), )
    CXXFLAGS += -msse
  else
    CXXFLAGS += -msse2
  endif
  CXXFLAGS += -mfpmath=sse -pthread
  CPPFLAGS += -D__LITTLE_ENDIAN__
  ifeq ($(DATAMODEL), ILP32)  
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=32
    CXXFLAGS += -m32
    LDFLAGS = -m32
    ASFLAGS = --32
    SRCS += ffi_stub_freebsd.s
  else
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=64
    CXXFLAGS += -m64
    LDFLAGS = -m64
    ASFLAGS = --64
    SRCS += ffi_stub_freebsd64.s
  endif
  LDLIBS = -pthread
endif

ifneq (, $(findstring OpenBSD, $(UNAME)))
  ifeq ($(shell $(CXX) -dumpspecs | grep 'march=native'), )
    ifeq ($(DATAMODEL), ILP32)  
      CXXFLAGS += -march=i686
    endif
  else
    CXXFLAGS += -march=native
  endif
  ifeq ($(shell dmesg | grep -i sse2), )
    CXXFLAGS += -msse
  else
    CXXFLAGS += -msse2
  endif
  CXXFLAGS += -mfpmath=sse -pthread
  CPPFLAGS += -D__LITTLE_ENDIAN__ -DNO_TLS
  ifeq ($(DATAMODEL), ILP32)  
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=32
    CXXFLAGS += -m32
    LDFLAGS = -m32
    ASFLAGS = --32
    SRCS += ffi_stub_openbsd.s
  else
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=64
    CXXFLAGS += -m64
    LDFLAGS = -m64
    ASFLAGS = --64
    SRCS += ffi_stub_openbsd64.s
  endif
  LDLIBS = -pthread
endif

ifneq (, $(findstring Darwin, $(UNAME)))
  CXXFLAGS += -arch i386 -msse2 -mfpmath=sse
  CPPFLAGS += -DNO_TLS
  SRCS += ffi_stub_darwin.s
  ifneq (, $(USE_SDL))
    CPPFLAGS += -DUSE_SDL
    LDFLAGS = extension/SDL/darwin/i386/SDLmain.o -framework SDL -framework Cocoa 
  endif
endif

[SNIP]

clean:
 rm -f *.o *.d
 rm -f $(HOME)/.ypsilon/*.cache 
 rm -f $(HOME)/.ypsilon/*.time

[SNIP]

x86/amd64大好きらしい，cleanは$(HOME)までお掃除する親切設計． :DDD

NetSurf / FrameBuffer #2

今日もframe buffer portをモニョった．

FTC_CMapCache_Lookup()でsegvるのは，error handlingがタコだったのとフォントへのパスがhardcodedで間違ってたのが原因．で，まずはSDL+freetype on Xで動くようになった．


さすがに黄色過ぎるので，internal pixel-colour変換を直すと，テキストの色は正しくなった．



endian dependな部分は泥臭くもあり，面白くもある．変な風にinternal pixel-colour変換がぶっ壊れると色がぶっ飛ぶ． :DDD

 02/28 01:24:33 hiyuh
    any idea? http://dev.gentoo.gr.jp/~hiyuh/misc/BE2.patch
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-BE2.png
 02/28 01:25:15 hiyuh
    it looks like only image ablend is broken, I guess.
 02/28 01:25:54 Kinnison
    looks like that
 02/28 01:26:13 kyllikki
    blue and green traded in your pixel to colour
 02/28 01:32:15 hiyuh
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-BE2-web-colors.png
 02/28 01:32:35 hiyuh
    text color is correct?
 02/28 01:33:03 kyllikki
    yes
 02/28 01:33:29 kyllikki
    the alpha blending is broken because the values its reading in to
    mix are wrong
 02/28 01:34:23 tlsa
    opaque images are wrong too
 02/28 01:34:33 hiyuh
    wtf :)
 02/28 01:34:57 tlsa
    well the screenshot is opaque, so is the logo image
 02/28 01:35:20 kyllikki
    I have no idea then
 02/28 01:35:38 kyllikki
    maybe the image formatters are getting it wrong on big endian systems?
 02/28 01:35:58 tlsa
    they'd be bust when he runs nsgtk
 02/28 01:38:40 hiyuh
    nsgtk works correctly on BE.
 02/28 01:40:11 tlsa
    there's something more wrong than just channel swapping
 02/28 01:40:36 tlsa
    cos the logo in the download box and the logo in the mast head should
    be the same colour
 02/28 01:40:46 tlsa
    but they are completely different
 02/28 01:45:01 tlsa
    actually, that's cos the background is different and the images are
    incorrectly getting alpha values other than opaque
 02/28 01:47:36 tlsa
    does the gtk build swap bitmap data round on BE?
 02/28 01:49:11 tlsa
    cos it looks perfect except for bitmaps
 02/28 01:54:21 hiyuh
    IIRC, nsgtk's image problems on BE was only in libnsgif code base
    (maybe it was in netsurf/image/gifread.c).
 02/28 01:56:37 tlsa
    well there's something certainly wrong with images
 02/28 01:56:50 tlsa
    and nothing wrong with text colours
 02/28 01:57:20 hiyuh
    true

と言う訳で，もう少しゴニョる必要があるのだったのだった． :)

NetSurf / FrameBuffer

#netsurfがframbuffer portで盛り上がっていたので，モニョる． :DDD

 02/26 21:01:19 hiyuh
    what does NETSURF_FB_FRONTEND=able mean?
 02/26 21:01:50 hiyuh
    runtime linux/sdl detection?
 02/26 21:02:29 tlsa
    to pick whether to build nsfb for the linux, able or other framebuffer
 02/26 21:02:54 kyllikki
    the list is now able, sdl, linux and vnc
 02/26 21:03:16 kyllikki
    sdl, linux and vnc are mostly what you will be interested in

 02/26 21:24:47 hiyuh
    nsfb-{sdl,linux} doesn't work here. :(
 02/26 21:26:09 rjek
    You won't get much help without details :)
 02/26 21:26:54 hiyuh
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-linux-r6625-fsckedup.jpg

 02/26 21:27:11 hiyuh
    color is fscked up completely. :)
 02/26 21:27:22 rjek
    Oh, an endianess problem.
 02/26 21:27:30 rjek
    TTOTD: Don't use big-endian machines.
 02/26 21:27:33 rjek
    :)
 02/26 21:28:09 hiyuh
    keyboard/mouse doesn't work too, so I did force powerdown this
    powerbook. :DDD
 02/26 21:29:22 hiyuh
    tested only x86 boxes?
 02/26 21:29:27 rjek
    And ARM.
 02/26 21:29:33 rjek
    Extensively on ARM, in fact.
 02/26 21:29:39 hiyuh
    ah, k
 02/26 21:31:10 jmb
    awesome
 02/26 21:31:17 jmb
    kyllikki: that rocks
 02/26 21:41:02 jmb
    hiyuh: I assume keyboard/mouse work correctly under sdl?
 02/26 21:43:45 jmb
    as for endianness, it's likely in the plotters
 02/26 21:45:18 hiyuh
    jmb: sadly, nope. sdl's one said "Unable to init SDL: Unable to open
    mouse" then segv immediately (was tested on X/fbconsole).
 02/26 21:45:29 jmb
    hiyuh: oddness
 02/26 21:46:59 jmb
    hiyuh: I assume other SDL apps work?
 02/26 21:47:16 hiyuh
    jmb: let me check
 02/26 21:47:51 jmb
    hiyuh: because the SDL_Init() call we have is entirely standard :)
 02/26 21:51:09 hiyuh
    jmb: it works on X, but it doesn't work on fb. maybe, causes of
    "sdl's ones didn't work on X/fbconsole" are different.
 02/26 21:52:13 jmb
    hiyuh: right
 02/26 21:57:48 hiyuh
    jmb: I guess X blocks mouse device access from SDL when I was on
    fbconsole, I'll check w/o running X (no VT switch).
 02/26 21:57:50 jmb
    there. updated the application
 02/26 21:58:02 jmb
    hiyuh: wouldn't surprise me
 02/26 21:58:09 hiyuh
    yup, bbl

 02/27 00:17:11 hiyuh
    jmb: cause of SDL_init error comes from my udev rules were
    fscked up, sorry. even though, sdl's one still rocks. :)
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-sdl-r6625-fsckedup-270.jpg

 02/27 00:18:34 Kinnison
    hiyuh: are colours in web pages wrong too?
 02/27 00:18:40 Kinnison
    Or just the furniture?
 02/27 00:21:05 hiyuh
    nope, it can not show any page ATM.
 02/27 00:21:51 Kinnison
    Odd
 02/27 00:21:56 Kinnison
    why not?
 02/27 00:23:24 tlsa
    Kinnison: web page colours were wrong in is photo:
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-linux-r6625-fsckedup.jpg
 02/27 00:27:06 Kinnison
    hmm
 02/27 00:27:39 Kinnison
    presumably this is kyllikki needing to support endianness stuff in
    his plotters?
 02/27 00:28:54 hiyuh
    fb_plotters_ablend()?
 02/27 00:30:37 Kinnison
    that's the alphablend isn't it?
 02/27 00:31:16 hiyuh
    I guess. it calculates r/g/b.
 02/27 00:50:09 kyllikki
    hi
 02/27 00:50:14 tlsa
    re k
 02/27 00:50:59 kyllikki
    right for big endien the least invasive way is to have different
    plotter c files built
 02/27 00:51:44 kyllikki
    e.g. fb_32bpp_plotters_be.c
 02/27 00:52:14 kyllikki
    because although the machines words are BE it appears the framebuffer
    display is LE
 02/27 00:52:39 kyllikki
    I suppose I could make it generic but...
 02/27 00:52:44 rjek
    How much of the code is actually different?
 02/27 00:52:47 rjek
    Might #ifdefing be better?
 02/27 00:53:08 kyllikki
    rjek: I really didnt want a load more #ifdeffery
 02/27 00:53:20 rjek
    Well, if large bits of the function will be different, I agree.
 02/27 00:53:30 kyllikki
    I am thinking of ways to remove the existing ifdefery
 02/27 00:53:52 kyllikki
    rjek: its every time an output colour is computed
 02/27 00:54:04 kyllikki
    so its not everso often
 02/27 00:57:04 kyllikki
    no, i see it
 02/27 00:57:08 kyllikki
    I can generalise it
 02/27 00:57:24 kyllikki
    in fact i ought to
 02/27 01:02:11 tlsa
    is it easy to add the rest of those pointers?
 02/27 01:06:42 kyllikki
    what #define can i use to determine endiness at compile time?
 02/27 01:09:55 hiyuh
    ? http://dev.gentoo.gr.jp/~hiyuh/misc/netsurf-gifread-try2fixonBE.diff
 02/27 01:11:02 kyllikki
    cool
 02/27 01:14:53 kyllikki
    try that?
 02/27 01:15:04 kyllikki
    I *think* my shifts are right
 02/27 01:15:50 kyllikki
    you get to test if #if __BYTE_ORDER == __BIG_ENDIAN is right
 02/27 01:16:45 hiyuh
    ACK
 02/27 01:19:38 *
    kyllikki waits paitently

 02/27 01:29:08 hiyuh
    lol
 02/27 01:29:09 hiyuh
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-sdl-r6635-onX-fsckedup.jpg

 02/27 01:29:46 hiyuh
    mouse/keyboard works. :)
 02/27 01:29:49 kyllikki
    hmm thats 32bpp?
 02/27 01:30:12 hiyuh
    dunno, just run nsfb on X.
 02/27 01:30:23 kyllikki
    well 32bpp is the default
 02/27 01:32:49 hiyuh
    let me try -linux.

 02/27 03:39:52 hiyuh
    on 32bpp nvidiafb, -linux shows red screen, keyboard/mouse doesn't
    work and cpu usage goes 100%  then I did force poweroff.
 02/27 03:40:01 hiyuh
    FYI, generic ppc machine uses offb which is 8bpp by default.
 02/27 03:40:05 hiyuh
    kyllikki: ^^
 02/27 03:40:39 kyllikki
    right, the 8bpp plotters may indeed be funted
 02/27 03:41:07 kyllikki
    hiyuh: I will take a look, maybe later maybe morrow
 02/27 03:41:15 kyllikki
    tired atm
 02/27 03:41:20 hiyuh
    k, thx
 02/27 03:41:24 kyllikki
    np

つーわけで，次回に持ち越し．
今のところ，一番まともなのは-sdlを32bpp nvidiafbで動かす場合かな．
nouveauの中の人は{nvidia,riva}fbはstateがゴチャゴチャになるからofonlyにしろって言うし，offbは32bppにならねーし，どーすっか．


で，NETSURF_FB_FONTLIB=freetypeにしたら，FTC_CMapCache_Lookup()でSEGVるのを発見．
gcc-4.3.3のbugかもしれんので，熟成の方向で． :P

tanslate(mercurial_ref, "ja_JP.UTF-8");

例のAでLな"ぷろじぇくつ"の残務も一段落したし，matsuu先生がブツの日本語訳を御所望なのでモニョる．
PowerBookにmedia-gfx/inkscapeをemergeするのはgnome depでコンパイルがダルいので，会社のパソコンにWindows版のinkscapeをぶち込んで仕事をしているフリをする． :DDD

で，出来たので晒す．


もっと大きいのが欲しいひとはこことここにあるので，御自由にどうぞ．
SVGはここに突っ込んだ．訳がヘチョいのとフォントがMS-Gothicになってるのが御愛嬌と言うことで． :P

emerge nouveau

AでLな"ぷろじぇくつ"に20kLOC overのVHDLを書きまくって，なんとか終わったのでnouveauで遊ぶ．

一応，upstream(?)のもあるにはあるが頑なにGallium3D対応にしようとしないので，今までmedia-libs/mesaだけ野良buildしていたがebuildにしてみた．proj/x11.gitとかからlive ebuildをパクってきて，モニョる． :DDD

まだTTMがアレなので，アレだのう． :S

if (!open("/dev/code", O_RDONLY)) { ...; }

NWCCの中の人とのメールの一部．

俺の好きなマイナーなブツに限らず，dev codeを拝めないことは良くある．メジャー/マイナーに関わらず，dev codeは爆弾な訳で，だからこそ見る側からすれば面白かったりするのだが，出す方は迷いもある．作り手である分，被害が具体的に予想出来てしまうのが原因，多分．

DSCMで気軽にブツを晒せる昨今になっても，changesetを綺麗にしてから出直して来いとか言ってrejectするメジャードコロでもあるまいし，自家製爆弾くらいを公開したって別に良くね？一つや二つ程度の地雷を踏んだ程度でupstreamの追っかけを止めるくらいなら，最初っから追っかけなんかやってんな，と．LICENSEは読んだか？ちゃんと，「爆発しても知らねーからな！！1」って書いてあるよ，だいたい．爆弾だったとき文句を言われのが嫌？別に爆弾じゃなくても文句なんていつも言うだろ，実際． :DDD