USE=-gold emerge sys-devel/binutils

　ボブ「やぁ，ジョニー，聞いてくれよ．」
ジョニー「なんだい，ボブ．」
　　ボブ「IUSE=goldなsys-devel/binutilsを見つけたので，chrootもせずにemergeしたんだ．」
ジョニー「へぇ，それはなんともricerらしいじゃないか．」
　　ボブ「だけどさ，続いてemergeしようとしたsys-apps/shadowのeconfがコケるんだ．」
ジョニー「それはまたどうして？」
　　ボブ「僕も変だなと思って，手元の自分のCのプログラムをコンパイルしてみたんだ．」
ジョニー「それで？」
　　ボブ「なんと何もコンパイル出来なくなってたんだよ！」
ジョニー「なんてこった！」
　　ボブ「慌ててUSE=-goldでsys-devel/binutilsをemergeしなおそうとしたんだけど．」
ジョニー「ダメだったと．」
　　ボブ「そうなんだ．」
ジョニー「なるほど．」
　　ボブ「なぁ，ジョニー，どうしたいいと思う？」
ジョニー「そんな時はricerなオレ達の強い味方，tinderbox.dev.gentoo.orgの出番さ．」
　　ボブ「何だいそれは？」
ジョニー「systemでstableなブツやクロスコンパイラのバイナリなんかを提供しているトコさ．」
　　ボブ「へぇ，普段自前でしかコンパイルしないから知らなかったよ．」
ジョニー「で，コイツをPORTAGE_BINHOSTで指定して-gKでemergeすれば良いんじゃないかな？」
　　ボブ「具体的には僕の場合はどうやるんだい？」
ジョニー「君はなぜかppc32だったよね？」
　　ボブ「うん，x86が嫌いだからね．」
ジョニー「ならこうさ！」

PORTAGE_BINHOST=http://tinderbox.dev.gentoo.org/default-linux/powerpc/ppc32 \
    emerge -gK =sys-devel/binutils-2.18-r3

　　ボブ「へぇ，いつもemergeするのとあんまり変わらないね．」
ジョニー「これで少し古いけどsys-devel/binutilsは治ったハズだよ．」
　　ボブ「なるほど，これで改めてUSE=-goldでsys-devel/binutilsをemergeすれば良いんだね！」
ジョニー「そうさ，簡単だろ？」
　　ボブ「ああ，やっぱりGentooは最高だね！」

Barcamp.Tokyo[2009] = BenTou + Curry;

waitingだったんだけど，「それでも大丈夫だから来い」みたいなことを言われたのでBarcamp Tokyo 2009に行ってきた．
TLUG並に外国人参加率が高くて，そこら中でネイティブっぽい人達の英語が炸裂してて，俺もPowerBoook弄ってまともに話を聞いていない事も相俟って当社比2倍で訳分からんかった．

あるbrainstormingで「barcampの日本人参加率を上げようぜ」みたいなネタが出て，ありえないぐらいマシンガンかましている人がいたが，正直何を言いたいのかさっぱり聞き取れんかった．
これは新手のプレイだね，間違い無い．

つーか，良く考えたら何で日本人参加率を上げたいんだろう？
彼らが都合の良い英語をプロトコルに使って，実のある話が出来れば日本人参加率が低くても良さそうなもんだけどなぁ．
仮に日本語でのプレゼンやら質疑応答を許可したとしても，そこら中でマシンガンかましているのが大多数だったら，普段英語なんか使う機会が殆ど無い日本人の参加率が上がる訳無ぇだろ，とかここではdisってみる．
少なくとも俺には「郷には入れば郷に従え」ってのが強迫観念みたいに頭から離れんよ．

言い訳しておくと，俺はコードのコメントは悉く英語だし，情報が英語で書かれていても知りたい情報なら読むし，IRCで1337 speakでフザケてたりするけど，耳と口は英語化してないんだよなぁ．
大抵の日本人はコードのコメントは日本語だし，情報が英語で書かれていたら読むのを躊躇うし，IRCで1337 speakなんかしないので，もっと英語化はしていないと思うんよ．

だから，向こうがマシンガンを捨ててカタナに装備を変えるか，こっちがカタナを捨ててマシンガンを装備するかのどちらかをしないと同じ戦場でまともに戦えない．
で，不味い事にマシンガンの方が戦力的に見て圧倒的に有利と言う現状がある訳で，極一部のサムライはカタナを捨ててマシンガンを装備するけど，残りの人達はカタナを持ったまま突撃するか，出島を作って鎖国するか，カタナを捨てて畑を耕してる．

brainstormingは基本的に否定/批判を排したブツだから，その場でどうこうってのはやらなかったし，する気も無かったけど，あそこでマシンガンぶっ放してた人達は最初からマシンガンだけしか装備していなかったとか，ただ単にカタナで斬り合った経験が無いだけだったりしねぇ？
それを一方的に「fair playじゃねぇ！！1」とか言う気は無いし，俺はカタナが結構好きだから別に構わないけど，同じ戦場でまともに戦う事を一番に望んでいるなら，マシンガンをぶっ放してた方はカタナも装備してみようとか，カタナでしか斬り合いした事が無いならマシンガンでもぶっ放してみようとか，っつー言う気概くらいはあっても良いと思うんだよね．

そう言う意味では拙い日本語でコミュニケーションをしようとしてくれるガイジンさんにはとても感謝したいし，俺のbr0ken Englishでも良いなら受け答えしてあげたいと思う．
ま，中々巧く話が進まない所もあってもどかしいけど，だがそれが良い． :)

ああ，そうそう．昼飯の弁当と夕食のカレーはタダ飯だったのでこんなタイトルになってます．深い意味はありません． :DDD

wm.lineage->next();

graphvizがタルくなったので，inkscapeを乗り換えた．
んで，色着けて線が交わらない様にしてみた． :)
SVGはここに晒しておこう．
[using inkscape instead of graphviz, then colorize and flatten. :)
want SVG? here it is.]

線はそれなりに関連があるって事で，必ずしもforkやrewriteを意味する分けでは無かったりする．
タイル型WMでないモノも入っていたり，そもそもWMじゃないモノも入っているがそれなりに意味がある．
[lines just indicate their relation, not only fork/rewrite.
There is some non-tiling WMs, more over few ones are not WM.
But they're worth to mention for explaining about recent GUI improvement for experienced users.]

あとはmultitalkの資料が間に合うかどうかだな． :p
[hmm, making presentation 2D map by multitalk? oh well. :P]

TLUG.NomiKai++; synthSound(&hardware);

TLUGに行ってきた．
BarCamp-Tokyo2009の中の人がHypertextについて話してたのと，XMLとSQLの香りがするsemantic webの話だった．
皆さんはレイヤが高いですな，あいかわらず． :)
飲み会/二次会ではshojiさんのSunオフレコ話とかJARIさん（北欧のイケメン）のアレとか色々．

帰ってからmatsuuさんのBarCamp-Tokyo2009用の下ごしらえっぽいモノとして，それっぽいgraphvizな絵をでっち上げた．
多分，もうちっと弄る．


上の絵をでっち上げていたら，#vhdlでhardware sound synthesize野郎が現れていた． :DDD

05/10 03:54:30 mad
    I'm planning on making sound generation stuff
05/10 03:56:23 mad
    most of that stuff is based around a phase register being incremented
    by the frequency on each sound cycle (which is pretty low rate -
    typically around 44khz)
05/10 04:02:43 bpadalino
    sounds like a cordic should help you out
05/10 04:04:46 hiyuh
    cordic is not for making sound, imho.
05/10 04:09:48 hiyuh
    that sounds like singletone, variable freq in narrow range, and
    presicion is not so important.
05/10 04:10:38 hiyuh
    maybe, making rom-based nco is enough to do.
05/10 04:14:39 bpadalino
    i don't know if a saw wave would sound very good, but as a phase
    accumulator - a cordic sounds like it would work well
05/10 04:30:24 hiyuh
    I meant cordic is expensive for that use.
05/10 04:30:29 hiyuh
    and saw wave + filter for singletone is not a possibility, anyway.
05/10 04:32:34 hiyuh
    phase accum -> sin or cos rom in appropriate precision -> singletone,
    it's simple rom-based nco.
05/10 04:40:47 bpadalino
    you really think a cordic is that expensive ?
05/10 04:51:49 hiyuh
    bpadalino: yes
05/10 04:51:58 bpadalino
    interesting
05/10 04:55:54 bpadalino
    hiyuh, so if you wanted to create 20 tones, how would you go about
    doing that ?
05/10 04:57:07 hiyuh
    20 tones in same time?
05/10 04:57:31 bpadalino
    yeah
05/10 04:59:05 hiyuh
    these tones are elaborate-time fixed or run-time fixed?
05/10 05:00:05 hiyuh
    I meant these tones are fixed before logic synthesize, or not.
05/10 05:00:29 bpadalino
    runtime fixed tones .. frequency fixed before synthesis, but phase
    programmable ..
05/10 05:00:44 bpadalino
    and i want the sum of the 20 tones on the output
05/10 05:07:54 hiyuh
    you mean "amplitude * (sin(2*pi*f1*t + theta1(t)) + ... sin(2*pi*f20*t
    + theta20(t)))"?
05/10 05:09:10 bpadalino
    yeah
05/10 05:10:53 hiyuh
    if I were you, I'd like to make semi-fixed digital filter or just
    do IFFT.
05/10 05:12:42 bpadalino
    that's what i had figured before, but i was just curious what someone
    else might have thought
05/10 05:13:00 hiyuh
    heh
05/10 05:14:18 bpadalino
    i would like to do my own generic systolic FFT sometime ... i think
    that might be fun
05/10 05:16:23 mad
    the tones parameters are written to at performance time
05/10 05:18:05 mad
    It's for music generation, so the applicable freqs are about 20hz to
    20khz (although tones over something like 4khz aren't particularly
    musical)
05/10 05:19:17 anonissimus
    mad: but as harmonics they are
05/10 05:19:33 mad
    Precision has to be at least 1%, esp. in the "most common range"
    (around 50hz ~ 1000hz)
05/10 05:19:50 mad
    anonissimus: yeah, but those are generated from another process
05/10 05:21:16 anonissimus
    ah
05/10 05:21:38 anonissimus
    know more on music than on generting it with hardware :)
05/10 05:21:57 mad
    My plan is: start with pure phase accumulator, then twist the phase
    around in a couple of functions (incl. one that uses multiplication),
    then use sine wave/funky waveform LUT, apply volume and panning,
    sum the channels together, DAC
05/10 05:24:12 mad
    Uses about 140 bits of registers per channel
05/10 05:27:44 mad
    A real practical design would actually be sample based instead
    (with samples in RAM)
05/10 05:29:23 hiyuh
    you know, your plan violates my assumption that described in the
    above expr.
05/10 05:29:25 hiyuh
    so what I was saying is not good way for you.
05/10 05:29:59 mad
    mm, right
05/10 05:31:35 mad
    sound synthesis isn't so hard because the sampling rate is low
    anyways... and you can do it well in software if you have enough CPU
05/10 05:32:14 hiyuh
    yeah, that's why soft synth is popular atm.
05/10 05:32:40 mad
    no kidding, since it pretty much solves it

つまり，敢えてsoftware sound synthesizeしないっつーことですか？
そいつは物好きだなぁ． :)

MeasureSLOC(&AL9); /* 2009/04 */

AでLで9なdiffstat，4月分．
[diffstat for AL9, for 2009/04.]

 a/bench/BENCH_NARROWER.vhd      |  148 -------
 a/vhdl/CPUMP.vhd                |  275 --------------
 a/vhdl/NARROWER.vhd             |  418 ----------------------
 a/vhdl/WIDER.vhd                |  350 ------------------
 b/bench/BENCH_HS_BUS.vhd        |  105 +++++
 b/bench/BENCH_SB.vhd            |  218 +++++++++++
 b/bench/BENCH_UDACCUM.vhd       |  100 +++++
 b/vhdl/HS_BUS.vhd               |  328 +++++++++++++++++
 b/vhdl/SB_MASTER.vhd            |  629 +++++++++++++++++++++++++++++++++
 b/vhdl/SB_SLAVE.vhd             |  339 ++++++++++++++++++
 b/vhdl/TX_SRC_MUX.vhd           |  180 +++++++++
 b/vhdl/TX_SX_FEBE.vhd           |  338 ++++++++++++++++++
 b/vhdl/UDACCUM.vhd              |  219 +++++++++++
 bench/BENCH_BCMUX.vhd           |    7 
 bench/BENCH_BER_IF_REG.vhd      |   92 ++--
 bench/BENCH_LDPCDDB.vhd         |  471 +++++++++++++++----------
 bench/BENCH_LDPCEDB.vhd         |  398 ++++++---------------
 bench/BENCH_PE2RST.vhd          |   49 +-
 bench/BENCH_TX_SMAP.vhd         |   43 +-
 bench/METABENCH_LDPCDDB.vhd     |  161 ++------
 bench/METABENCH_LDPCEDB.vhd     |  140 ++-----
 bench/METAMETABENCH_LDPCDDB.vhd |  104 +++++
 bench/METAMETABENCH_LDPCEDB.vhd |    4 
 stim/STIM_PN_DATA.vhd           |  156 +++++++-
 stim/STIM_RX_DATA_CARR.vhd      |  139 ++++++-
 stim/STIM_TX_DATA_CARR.vhd      |  135 ++++++-
 vhdl/AFIFO.vhd                  |   30 +
 vhdl/BER_IF_REG.vhd             |  743 ++++++++++++++++++++--------------------
 vhdl/CLDPCDOP.vhd               |   11 
 vhdl/COMMON_TYPE_PKG.vhd        |    7 
 vhdl/DFE_NEGOTIATE.vhd          |  282 ++++++++++-----
 vhdl/ELDPCDII.vhd               |   21 -
 vhdl/FCOD.vhd                   |   24 -
 vhdl/HD2BO.vhd                  |  123 +++---
 vhdl/LDPCD.vhd                  |   35 -
 vhdl/LDPCE.vhd                  |   41 +-
 vhdl/LDPCEDB.vhd                |   30 +
 vhdl/LLR2SC.vhd                 |   57 ++-
 vhdl/PE2RST.vhd                 |  310 +++++++++++-----
 vhdl/PN_BLOB.vhd                |   89 +---
 vhdl/PN_NEGOTIATE.vhd           |  274 ++++++++++----
 vhdl/PSQUASH.vhd                |   72 ++-
 vhdl/S2BER_IF.vhd               |   66 +--
 vhdl/SB2SSB.vhd                 |   83 +++-
 vhdl/SBSSBDD.vhd                |    8 
 vhdl/SFIFO.vhd                  |   16 
 vhdl/VTQUEUE.vhd                |    4 
 47 files changed, 4939 insertions(+), 2933 deletions(-)

やっぱ，10kSLOC逝ってないYO!!1 :DDD
[ZOMG, under 10kSLOC AGAIN!!1 :DDD]

VHDL -= function; VHDL -= procedure;

#vhdlにて，functionもprocedureもいらねぇだろうと寝言を言う野郎が出現．
[At #vhdl, t3h guy shoutz "no function and no procedure FTW!!1". So I'd have to say WTF.]

04/30 20:42:47 algoboy
    i need to create a load register, that load the value on a load
    signal, should the register be combinational or clocked? It has to
    hold the loaded values on the output until new values are loaded.
04/30 22:31:38 hw__
    I've been told that everywhere I call a function, the function is
    replaced by logic. So when I call 5 times a function I've 5 times
    the same logic in my FPGA. How about procedures? Does it depend on
    the class of formal/actual parameter?
04/30 23:51:23 algoboy
    hw__ : it depends on where you are calling the functions. If you
    write code that describes a circuit to do 5xtimes your function in
    one clock cycle then it will generate 5 times the hardware. But if
    you instead create a FSM and call the same function from 5 different
    states it should be synthesized to 1 function hardware, depending
    on if the synthesizing tool can schedule the operation and reuse
    the same hardware.
04/30 23:54:05 algoboy
    also the difference between a procedure and a function is that
    functions have a return value, procedures don't.
04/30 23:55:30 hw__
    algoboy: procedures can have "results" as well: If you use "inout"
    or "out" for parameter mode
04/30 23:57:38 algoboy
    yes, but i was just telling the difference between a procedure and
    function. a procedure doesn't return a value. The same as a void
    function in c/c++.
04/30 23:57:57 hiyuh
    no
04/30 23:58:47 algoboy
    no???
05/01 00:03:42 hiyuh
    procedure is procedure. function is function. not less, not more.
05/01 00:03:50 hiyuh
    if you really want to know what they are, read VHDL LRM or general
    CS book like MIT SICP.
05/01 00:08:56 algoboy
    yes a procedure is a procedure and a function is a function. I was
    just telling the difference between them. You can always transform
    a procedure to a function and a function to a procedure.
05/01 00:10:58 algoboy
    I don't see any benefit of using procedures and functions in VHDL. If
    you wan to create a "function" in VHDL create a circuit instead,
    sequential or combinational. This is a much better approach.
05/01 00:12:29 hiyuh
    whut?
05/01 00:13:14 hiyuh
    then, haven't you ever read the two-process method paper?
05/01 00:14:58 NULL[0]
    algoboy: are you a troll ?
05/01 00:15:47 hiyuh
    NULL[0]: i dont think so. :)
05/01 00:16:47 NULL[0]
    hiyuh: if you read his question, and the comments he made, I would
    not be surprised
05/01 00:17:16 longcat
    meh
05/01 00:18:28 algoboy
    hiyuh: Gaisler's two process method?? What does that have to do with
    procedures and functions.
05/01 00:19:00 hiyuh
    algoboy: yup.
05/01 00:19:33 algoboy
    yes i have, i uses the two process method almost all the time. But
    i never use functions and procedures. So i don't get your question.
05/01 00:20:49 hiyuh
    well, are you codin' vhdl as daily job, or?
05/01 00:21:18 algoboy
    no
05/01 00:21:53 algoboy
    i'm still a student
05/01 00:23:53 hiyuh
    okay, I got it, you should code more to realize why function/procedure
    are.
05/01 00:23:58 hiyuh
    I'm always codin' vhdl as daily job. no function/procedure is
    nightmare for me.
05/01 00:26:15 algoboy
    The only benefit i could think of is if you create your own library
    so that you can reuse.
05/01 00:31:21 hiyuh
    what you're saying looks like "always code by using machine language
    in HEX editor" to me.
05/01 00:31:27 hiyuh
    or, sounds like "paste same code from existing ones, b/c I don't
    like any abstraction."
05/01 00:33:04 drichards
    isn't abstraction the whole point of an HDL?
05/01 00:33:37 MatthiasM
    I use functions for simple things - like counting leading zeros etc
05/01 00:34:06 algoboy
    VHDL is not a programming language so i wouldn't write any machine
    code. I use VHDL to describe hardware and and prefer to work on the
    RTL level.
05/01 00:34:27 MatthiasM
    or procedures for updating more complex counters like this: lsb <=
    (lsb + inc) mod X; msb <= msb + (lsb + inc) / X;
05/01 00:35:06 *
    hiyuh lolz @ "VHDL is not a programming language"
05/01 00:35:15 MatthiasM
    functions are much more flexible as you can decide where to store
    the return value when you call it (or use it directly in an IF)
05/01 00:35:51 algoboy
    hiyuh: :/
05/01 00:35:59 MatthiasM
    procedures can have more then one return value - but you must decide
    if the values are passed/returned as signal or variable
05/01 00:36:43 MatthiasM
    all functions and procedures are basicly combinatorical logic -
    if you need something with a clock - write a new entity
05/01 00:37:22 algoboy
    MatthiasM: so why not write combinatorial logic all the time?
05/01 00:37:35 MatthiasM
    algoboy: LOL
05/01 00:37:50 algoboy
    MatthiasM: instead of a function or procedure
05/01 00:38:29 MatthiasM
    the example of the procedure above - is about ~10 lines of code -
    I need it in 4 places - calling it takes 1 line of code
05/01 00:38:45 MatthiasM
    and it even works when the bit width of the busses are different
    for each call
05/01 00:39:42 drichards
    which is why I like subprogs
05/01 00:39:55 algoboy
    MatthiasM: create the same procedure as a circuit. Use generate to
    generate x instances and also use genric.
05/01 00:39:55 drichards
    they can react to the act bus width, register width, etc.
05/01 00:39:58 algoboy
    the same thing
05/01 00:40:57 MatthiasM
    algoboy: I can call a function/procedure inside a clocked process
    and inside nested control edges - this makes it very easy to write
    complex logic with sequential source code
05/01 00:41:34 MatthiasM
    as a designer I want to write code that is A) easy to write B)
    easy to read C) easy to change
05/01 00:41:56 MatthiasM
    and it's the tools job to create an efficient logic implementation
    based on my source code
05/01 00:43:10 MatthiasM
    ofcourse you have to be careful to not create to wide logic functions
    - which can easily happen if you nest IFs - or check the result of
    combinatorical functions (like "IF x+1 == y THEN .... END IF;")
05/01 00:43:43 MatthiasM
    algoboy: if you understand these - then you can create a complex
    design in a short time
05/01 00:43:51 algoboy
    MatthiasM: i prefere to write synthesizable code, targeting low power,
    low area. Using higher abstraction you rely much on the synthesizing
    tool to do the job for you.
05/01 00:44:10 NULL[0]
    ...
05/01 00:44:32 MatthiasM
    yep - that's why I use Quartus - it's synthesizer is very good -
    it's very hard to create more efficient logic by hand
05/01 00:45:54 algoboy
    oh, fpga synthesizing is one thing, but i am running asic flow and
    it is a huge difference.
05/01 00:46:19 tzanger
    MatthiasM: quartus is for atmel, right?
05/01 00:46:27 MatthiasM
    Altera
05/01 00:46:30 algoboy
    yes
05/01 00:46:35 algoboy
    altera
05/01 00:47:32 tzanger
    er altera
05/01 00:47:33 tzanger
    duh
05/01 00:47:41 tzanger
    I knew it was an A. :-)
05/01 00:47:47 algoboy
    :p
05/01 00:47:49 *
    hiyuh petz NULL[0]. :)
05/01 00:48:09 MatthiasM
    algoboy: take a look at some old code: http://pastebin.com/d418ebc0e
05/01 00:49:10 MatthiasM
    the production code uses constants instead of hard coded values
    ofcourse
05/01 00:52:14 algoboy
    MatthiasM: VGA controller?
05/01 00:52:25 MatthiasM
    sync generator for DVI
05/01 00:52:34 MatthiasM
    (VGA doesn't use DE signal)
05/01 00:52:52 algoboy
    oh :)
05/01 00:53:17 MatthiasM
    but it started as VGA generator - that's why the clock is called
    vga_clk
05/01 00:53:41 hiyuh
    rename FTW!!1 :)
05/01 00:54:15 MatthiasM
    algoboy: see the splitted counter in line 28 and the compare in line
    35 ? the current code uses procedures for increment and a function
    for compare
05/01 00:54:20 algoboy
    MatthiasM: that is nice code :) no functions or procedures :)
05/01 00:54:45 MatthiasM
    that way I can just write "IF compare(row_cnt2, row_cnt1, 12, 805)
    then .... end if;"
05/01 00:56:28 MatthiasM
    algoboy: eg http://pastebin.com/d7c8c5b34
05/01 00:56:41 MatthiasM
    much more readable
05/01 00:57:52 algoboy
    yes it is, if you know what the functions does.
05/01 00:58:18 MatthiasM
    that's why you can put comments into the VHDL files
05/01 01:00:08 algoboy
    :p
05/01 01:00:24 *
    hiyuh sticks more popcorn to the microwave.
05/01 01:00:40 *
    MatthiasM steals hiyuh's popcorn
05/01 01:01:00 hiyuh
    lol
05/01 01:01:16 MatthiasM
    :DD

ポップコーンを喰えたので良しとする． :DDD
[PLESIOUS POPCORN TIME, YUM!!1 :DDD]

updateCRC(&CRC, &byte);

ちとCRCをムニャる必要が出て来たので，例の本をゴニョると，byte streamに対して計算するアルゴリズムが載っていたので，2時間くらいモニョモニョしてVHDLで実装した．

先ず，popularな生成多項式をWikipediaからパクってきてpackageに．

library ieee;
use ieee.std_logic_1164.all;

package CRC_GENERATOR_PKG is

 constant cCRC_1_GENERATOR              : std_logic_vector;
 constant cCRC_4_ITU_GENERATOR          : std_logic_vector;
 constant cCRC_5_ITU_GENERATOR          : std_logic_vector;
 constant cCRC_5_USB_GENERATOR          : std_logic_vector;
 constant cCRC_6_ITU_GENERATOR          : std_logic_vector;
 constant cCRC_7_GENERATOR              : std_logic_vector;
 constant cCRC_8_ATM_GENERATOR          : std_logic_vector;
 constant cCRC_8_CCITT_GENERATOR        : std_logic_vector;
 constant cCRC_8_Dallas_Maxim_GENERATOR : std_logic_vector;
 constant cCRC_8_GENERATOR              : std_logic_vector;
 constant cCRC_8_SAE_J1850_GENERATOR    : std_logic_vector;
 constant cCRC_10_GENERATOR             : std_logic_vector;
 constant cCRC_11_GENERATOR             : std_logic_vector;
 constant cCRC_12_GENERATOR             : std_logic_vector;
 constant cCRC_15_CAN_GENERATOR         : std_logic_vector;
 constant cCRC_16_CCITT_GENERATOR       : std_logic_vector;
 constant cCRC_16_DNP_GENERATOR         : std_logic_vector;
 constant cCRC_16_IBM_GENERATOR         : std_logic_vector;
 constant cCRC_24_Radix_64_GENERATOR    : std_logic_vector;
 constant cCRC_30_GENERATOR             : std_logic_vector;
 constant cCRC_32_IEEE_802_3_GENERATOR  : std_logic_vector;
 constant cCRC_32_Castagnoli_GENERATOR  : std_logic_vector;
 constant cCRC_32_Koopman_GENERATOR     : std_logic_vector;
 constant cCRC_64_ISO_3309_GENERATOR    : std_logic_vector;
 constant cCRC_64_ECMA_182_GENERATOR    : std_logic_vector;

end package CRC_GENERATOR_PKG;

package body CRC_GENERATOR_PKG is

 type tCRC_TYPE is (
  CRC_1,
  CRC_4_ITU,
  CRC_5_ITU,
  CRC_5_USB,
  CRC_6_ITU,
  CRC_7,
  CRC_8_ATM,
  CRC_8_CCITT,
  CRC_8_Dallas_Maxim,
  CRC_8,
  CRC_8_SAE_J1850,
  CRC_10,
  CRC_11,
  CRC_12,
  CRC_15_CAN,
  CRC_16_CCITT,
  CRC_16_DNP,
  CRC_16_IBM,
  CRC_24_Radix_64,
  CRC_30,
  CRC_32_IEEE_802_3,
  CRC_32_Castagnoli,
  CRC_32_Koopman,
  CRC_64_ISO_3309,
  CRC_64_ECMA_182
 );

 type tCRC_LENGTH is array (tCRC_TYPE) of integer range 1 to 64;
 constant cCRC_LENGTH : tCRC_LENGTH := (
  CRC_1              =>  1,
  CRC_4_ITU          =>  4,
  CRC_5_ITU          =>  5,
  CRC_5_USB          =>  5,
  CRC_6_ITU          =>  6,
  CRC_7              =>  7,
  CRC_8_ATM          =>  8,
  CRC_8_CCITT        =>  8,
  CRC_8_Dallas_Maxim =>  8,
  CRC_8              =>  8,
  CRC_8_SAE_J1850    =>  8,
  CRC_10             => 10,
  CRC_11             => 11,
  CRC_12             => 12,
  CRC_15_CAN         => 15,
  CRC_16_CCITT       => 16,
  CRC_16_DNP         => 16,
  CRC_16_IBM         => 16,
  CRC_24_Radix_64    => 24,
  CRC_30             => 30,
  CRC_32_IEEE_802_3  => 32,
  CRC_32_Castagnoli  => 32,
  CRC_32_Koopman     => 32,
  CRC_64_ISO_3309    => 64,
  CRC_64_ECMA_182    => 64
 );

 type tCRC_GENERATOR is array (tCRC_TYPE) of std_logic_vector(64 downto 0);
 constant cCRC_GENERATOR : tCRC_GENERATOR := (
  CRC_1              =>
   -- x^1  + x^0
   (64 downto  1+1 => '0') & "11",
  CRC_4_ITU          =>
   -- x^4  + x^1  + x^0
   (64 downto  4+1 => '0') & "10011",
  CRC_5_ITU          =>
   -- x^5  + x^4  + x^2  + x^0
   (64 downto  5+1 => '0') & "110101",
  CRC_5_USB          =>
   -- x^5  + x^2  + x^0
   (64 downto  5+1 => '0') & "100101",
  CRC_6_ITU          =>
   -- x^6  + x^1  + x^0
   (64 downto  6+1 => '0') & "1000011",
  CRC_7              =>
   -- x^7  + x^3  + x^0
   (64 downto  7+1 => '0') & "10001001",
  CRC_8_ATM          =>
   -- x^8  + x^2  + x^1  + x^0
   (64 downto  8+1 => '0') & "100000111",
  CRC_8_CCITT        =>
   -- x^8  + x^7  + x^3  + x^2  + x^0
   (64 downto  8+1 => '0') & "110001101",
  CRC_8_Dallas_Maxim =>
   -- x^8  + x^5  + x^4  + x^0
   (64 downto  8+1 => '0') & "100110001",
  CRC_8              =>
   -- x^8  + x^7  + x^6  + x^4  + x^2  + x^0
   (64 downto  8+1 => '0') & "111010101",
  CRC_8_SAE_J1850    =>
   -- x^8  + x^4  + x^3  + x^2  + x^0
   (64 downto  8+1 => '0') & "100011101",
  CRC_10             =>
   -- x^10 + x^9  + x^5  + x^4  + x^1  + x^0
   (64 downto 10+1 => '0') & "11000110011",
  CRC_11             =>
   -- x^11 + x^9  + x^8  + x^7  + x^2  + x^0
   (64 downto 11+1 => '0') & "101110000101",
  CRC_12             =>
   -- x^12 + x^11 + x^3  + x^2  + x^1  + x^0
   (64 downto 12+1 => '0') & "1100000001111",
  CRC_15_CAN         =>
   -- x^15 + x^14 + x^10 + x^8  + x^7  + x^4  + x^3  + x^0
   (64 downto 15+1 => '0') & "1100010110011001",
  CRC_16_CCITT       =>
   -- x^16 + x^12 + x^5  + x^0
   (64 downto 16+1 => '0') & "10001000000100001",
  CRC_16_DNP         =>
   -- x^16 + x^13 + x^12 + x^11 + x^10 + x^8  + x^6  + x^5  + x^2  + x^0
   (64 downto 16+1 => '0') & "10011110101100101",
  CRC_16_IBM         =>
   -- x^16 + x^15 + x^2  + x^0
   (64 downto 16+1 => '0') & "11000000000000101",
  CRC_24_Radix_64    =>
   -- x^24 + x^23 + x^18 + x^17 + x^14 + x^11 + x^10 + x^7  + x^6  + x^5
   --      + x^4  + x^3  + x^1  + x^0
   (64 downto 24+1 => '0') & "1100001100100110011111011",
  CRC_30             =>
   -- x^30 + x^29 + x^21 + x^20 + x^15 + x^13 + x^12 + x^11 + x^8  + x^7
   --      + x^6  + x^2  + x^1  + x^0
   (64 downto 30+1 => '0') & "1100000001100001011100111000111",
  CRC_32_IEEE_802_3  =>
   -- x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8  + x^7
   --      + x^5  + x^4  + x^2  + x^1  + x^0
   (64 downto 32+1 => '0') & "100000100110000010001110110110111",
  CRC_32_Castagnoli  =>
   -- x^32 + x^28 + x^27 + x^26 + x^25 + x^23 + x^22 + x^20 + x^19 + x^18
   --      + x^14 + x^13 + x^11 + x^10 + x^9  + x^8  + x^6  + x^0
   (64 downto 32+1 => '0') & "100011110110111000110111101000001",
  CRC_32_Koopman     =>
   -- x^32 + x^30 + x^29 + x^28 + x^26 + x^20 + x^19 + x^17 + x^16 + x^15
   --      + x^11 + x^10 + x^7  + x^6  + x^4  + x^2  + x^1  + x^0
   (64 downto 32+1 => '0') & "101110100000110111000110011010111",
  CRC_64_ISO_3309    =>
   -- x^64 + x^4  + x^3  + x^1  + x^0
   "10000000000000000000000000000000000000000000000000000000000011011",
  CRC_64_ECMA_182    =>
   -- x^64 + x^62 + x^57 + x^55 + x^54 + x^53 + x^52 + x^47 + x^46 + x^45
   --      + x^40 + x^39 + x^38 + x^37 + x^35 + x^33 + x^32 + x^31 + x^29
   --      + x^27 + x^24 + x^23 + x^22 + x^21 + x^19 + x^17 + x^13 + x^12
   --      + x^10 + x^9  + x^7  + x^4  + x^1  + x^0
   "10100001011110000111000011110101110101001111010100011011010010011"
 );

 constant cCRC_1_GENERATOR              : std_logic_vector := cCRC_GENERATOR(CRC_1             )(cCRC_LENGTH(CRC_1             ) downto 0);
 constant cCRC_4_ITU_GENERATOR          : std_logic_vector := cCRC_GENERATOR(CRC_4_ITU         )(cCRC_LENGTH(CRC_4_ITU         ) downto 0);
 constant cCRC_5_ITU_GENERATOR          : std_logic_vector := cCRC_GENERATOR(CRC_5_ITU         )(cCRC_LENGTH(CRC_5_ITU         ) downto 0);
 constant cCRC_5_USB_GENERATOR          : std_logic_vector := cCRC_GENERATOR(CRC_5_USB         )(cCRC_LENGTH(CRC_5_USB         ) downto 0);
 constant cCRC_6_ITU_GENERATOR          : std_logic_vector := cCRC_GENERATOR(CRC_6_ITU         )(cCRC_LENGTH(CRC_6_ITU         ) downto 0);
 constant cCRC_7_GENERATOR              : std_logic_vector := cCRC_GENERATOR(CRC_7             )(cCRC_LENGTH(CRC_7             ) downto 0);
 constant cCRC_8_ATM_GENERATOR          : std_logic_vector := cCRC_GENERATOR(CRC_8_ATM         )(cCRC_LENGTH(CRC_8_ATM         ) downto 0);
 constant cCRC_8_CCITT_GENERATOR        : std_logic_vector := cCRC_GENERATOR(CRC_8_CCITT       )(cCRC_LENGTH(CRC_8_CCITT       ) downto 0);
 constant cCRC_8_Dallas_Maxim_GENERATOR : std_logic_vector := cCRC_GENERATOR(CRC_8_Dallas_Maxim)(cCRC_LENGTH(CRC_8_Dallas_Maxim) downto 0);
 constant cCRC_8_GENERATOR              : std_logic_vector := cCRC_GENERATOR(CRC_8             )(cCRC_LENGTH(CRC_8             ) downto 0);
 constant cCRC_8_SAE_J1850_GENERATOR    : std_logic_vector := cCRC_GENERATOR(CRC_8_SAE_J1850   )(cCRC_LENGTH(CRC_8_SAE_J1850   ) downto 0);
 constant cCRC_10_GENERATOR             : std_logic_vector := cCRC_GENERATOR(CRC_10            )(cCRC_LENGTH(CRC_10            ) downto 0);
 constant cCRC_11_GENERATOR             : std_logic_vector := cCRC_GENERATOR(CRC_11            )(cCRC_LENGTH(CRC_11            ) downto 0);
 constant cCRC_12_GENERATOR             : std_logic_vector := cCRC_GENERATOR(CRC_12            )(cCRC_LENGTH(CRC_12            ) downto 0);
 constant cCRC_15_CAN_GENERATOR         : std_logic_vector := cCRC_GENERATOR(CRC_15_CAN        )(cCRC_LENGTH(CRC_15_CAN        ) downto 0);
 constant cCRC_16_CCITT_GENERATOR       : std_logic_vector := cCRC_GENERATOR(CRC_16_CCITT      )(cCRC_LENGTH(CRC_16_CCITT      ) downto 0);
 constant cCRC_16_DNP_GENERATOR         : std_logic_vector := cCRC_GENERATOR(CRC_16_DNP        )(cCRC_LENGTH(CRC_16_DNP        ) downto 0);
 constant cCRC_16_IBM_GENERATOR         : std_logic_vector := cCRC_GENERATOR(CRC_16_IBM        )(cCRC_LENGTH(CRC_16_IBM        ) downto 0);
 constant cCRC_24_Radix_64_GENERATOR    : std_logic_vector := cCRC_GENERATOR(CRC_24_Radix_64   )(cCRC_LENGTH(CRC_24_Radix_64   ) downto 0);
 constant cCRC_30_GENERATOR             : std_logic_vector := cCRC_GENERATOR(CRC_30            )(cCRC_LENGTH(CRC_30            ) downto 0);
 constant cCRC_32_IEEE_802_3_GENERATOR  : std_logic_vector := cCRC_GENERATOR(CRC_32_IEEE_802_3 )(cCRC_LENGTH(CRC_32_IEEE_802_3 ) downto 0);
 constant cCRC_32_Castagnoli_GENERATOR  : std_logic_vector := cCRC_GENERATOR(CRC_32_Castagnoli )(cCRC_LENGTH(CRC_32_Castagnoli ) downto 0);
 constant cCRC_32_Koopman_GENERATOR     : std_logic_vector := cCRC_GENERATOR(CRC_32_Koopman    )(cCRC_LENGTH(CRC_32_Koopman    ) downto 0);
 constant cCRC_64_ISO_3309_GENERATOR    : std_logic_vector := cCRC_GENERATOR(CRC_64_ISO_3309   )(cCRC_LENGTH(CRC_64_ISO_3309   ) downto 0);
 constant cCRC_64_ECMA_182_GENERATOR    : std_logic_vector := cCRC_GENERATOR(CRC_64_ECMA_182   )(cCRC_LENGTH(CRC_64_ECMA_182   ) downto 0);

end package body CRC_GENERATOR_PKG;

次に，生成多項式とbit per byteをgenericで指定して，例のアルゴリズムをそのままtwo-process手法で実装．

library ieee;
use ieee.std_logic_1164.all;
use work.CRC_GENERATOR_PKG.all;

package BYTE_CRC_PKG is

 component BYTE_CRC is
  generic (
   BPB       : integer range 1 to integer'high := 8;
   GENERATOR : std_logic_vector                := cCRC_16_CCITT_GENERATOR;
   ASYNC     : boolean                         := false
  );
  port (
   iCLK : in  std_logic;
   iCLR : in  std_logic;
   iINI : in  std_logic;
   iE   : in  std_logic;
   iD   : in  std_logic_vector(         BPB-1 downto 0);
   oE   : out std_logic;
   oD   : out std_logic_vector(         BPB-1 downto 0);
   oCRC : out std_logic_vector((GENERATOR'length-1)-1 downto 0)
  );
 end component BYTE_CRC;

end package BYTE_CRC_PKG;

package body BYTE_CRC_PKG is

 -- NOTE: This body should keep to be empty to stub.

end package body BYTE_CRC_PKG;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.CRC_GENERATOR_PKG.all;

entity BYTE_CRC is
 generic (
  BPB       : integer range 1 to integer'high := 8;
  GENERATOR : std_logic_vector                := cCRC_16_CCITT_GENERATOR;
  ASYNC     : boolean                         := false
 );
 port (
  iCLK : in  std_logic;
  iCLR : in  std_logic;
  iINI : in  std_logic;
  iE   : in  std_logic;
  iD   : in  std_logic_vector(         BPB-1 downto 0);
  oE   : out std_logic;
  oD   : out std_logic_vector(         BPB-1 downto 0);
  oCRC : out std_logic_vector((GENERATOR'length-1)-1 downto 0)
 );
begin
 A_BPB_CHECK : assert ((GENERATOR'length-1) mod BPB = 0)
  report BYTE_CRC'instance_name &
   "GENERATOR'length-1 should be congrunet to 0 modulo BPB!!1"
   severity error;
end entity BYTE_CRC;

architecture TP of BYTE_CRC is

 pure function fLEAD_BIT_INDEX (
  iX : std_logic_vector
 ) return integer is
 begin
  F_L : for l in iX'range loop
   if (iX(l) = '1') then
    return l;
   end if;
  end loop F_L;
  return -1;
 end function fLEAD_BIT_INDEX;

 type tCRC_REMAINDER is
  array (0 to 2**BPB-1) of
   std_logic_vector((GENERATOR'length-1)-1 downto 0);

 pure function fCRC_REMAINDER (
  iG : std_logic_vector
 ) return tCRC_REMAINDER is
  variable vLG            : integer range -1 to iG'length-1;
  variable vQ             : std_logic_vector(BPB-1 downto 0);
  variable vR             : std_logic_vector(vQ'length+(iG'length-1)-1 downto 0);
  variable vLR            : integer range -1 to vR'length-1;
  variable vG             : std_logic_vector(vR'range);
  variable vCRC_REMAINDER : tCRC_REMAINDER;
 begin
  vLG := fLEAD_BIT_INDEX(iG);
  F_Q : for Q in 0 to 2**vQ'length-1 loop
   vQ  := conv_std_logic_vector(Q, vQ'length);
   vR  := vQ & ((iG'length-1)-1 downto 0 => '0');
   vLR := fLEAD_BIT_INDEX(vR);
   W_R : while (vLR >= vLG) loop
    vG  :=
     (vG'length-1 downto vLR+1 => '0') &
     iG(vLG downto 0)                  &
     (vLR-vLG-1 downto 0 => '0');
    vR  := vR xor vG;
    vLR := fLEAD_BIT_INDEX(vR);
   end loop W_R;
   -- synthesis translate_off
   A_CRC_REMAINDER_CHECK :
    assert (vR(vR'length-1 downto iG'length-1) =
     (vR'length-1 downto iG'length-1 => '0'))
     report fCRC_REMAINDER'instance_name &
      "CRC remainder is out of range!!1"
     severity error;
   -- synthesis translate_on
   vCRC_REMAINDER(Q) := vR((iG'length-1)-1 downto 0);
  end loop F_Q;
  return vCRC_REMAINDER;
 end function fCRC_REMAINDER;

 constant cCRC_REMAINDER : tCRC_REMAINDER := fCRC_REMAINDER(GENERATOR);

 type tCRC is
  array (((GENERATOR'length-1)/BPB)-1 downto 0) of
   std_logic_vector(BPB-1 downto 0);

 type t is record
  E   : std_logic;
  D   : std_logic_vector(BPB-1 downto 0);
  RI  : std_logic_vector(BPB-1 downto 0);
  CRC : tCRC;
 end record t;

 constant c : t := (
  E   => '0',
  D   => (BPB-1 downto 0 => '0'),
  RI  => (BPB-1 downto 0 => '0'),
  CRC => (tCRC'range => (BPB-1 downto 0 => '0'))
 );

 signal g : t;
 signal r : t := c;

begin

 P_COMB : process (iINI, iE, iD, r)
  variable v : t := c;
 begin
  if (iINI = '1') then
   v.E  := '0';
   v.D  := (BPB-1 downto 0 => '0');
   v.RI := (BPB-1 downto 0 => '0');
   F_CRC_INITIALIZE : for i in tCRC'range loop
    v.CRC(i) := (BPB-1 downto 0 => '0');
   end loop F_CRC_INITIALIZE;
  elsif (iE = '1') then
   v.E  := '1';
   v.D  := iD;
   v.RI := iD xor r.CRC(tCRC'high);
   F_CRC_UPDATE : for i in tCRC'range loop
    if (i = tCRC'low) then
     v.CRC(i) :=
      cCRC_REMAINDER(conv_integer(unsigned(v.RI)))((i+1)*BPB-1 downto i*BPB);
    else
     v.CRC(i) :=
      r.CRC(i-1) xor
      cCRC_REMAINDER(conv_integer(unsigned(v.RI)))((i+1)*BPB-1 downto i*BPB);
    end if;
   end loop F_CRC_UPDATE;
  else
   v.E   := '0';
   v.D   := r.D;
   v.RI  := r.RI;
   v.CRC := r.CRC;
  end if;

  g  <= v;
  oE <= r.E;
  oD <= r.D;
  F_CRC_OUTPUT : for i in tCRC'range loop
   oCRC((i+1)*BPB-1 downto i*BPB) <= r.CRC(i);
  end loop F_CRC_OUTPUT;
 end process P_COMB;

 G_ASYNC : if (ASYNC = true) generate
 begin
  P_SEQ : process (iCLR, iCLK)
  begin
   if (iCLR = '1') then
    r <= c;
   elsif (iCLK'event and iCLK = '1') then
    r <= g;
   end if;
  end process P_SEQ;
 end generate G_ASYNC;

 G_SYNC : if (ASYNC = false) generate
 begin
  P_SEQ : process (iCLK)
  begin
   if (iCLK'event and iCLK = '1') then
    if (iCLR = '1') then
     r <= c;
    else
     r <= g;
    end if;
   end if;
  end process P_SEQ;
 end generate G_SYNC;

end architecture TP;

最後に，やる気の無いテストベンチをでっち上げ．

library ieee;
use ieee.std_logic_1164.all;
use work.CRC_GENERATOR_PKG.all;
use work.BYTE_CRC_PKG.all;

entity BENCH_BYTE_CRC is
begin
end entity BENCH_BYTE_CRC;

architecture BENCH of BENCH_BYTE_CRC is

 constant cCLK_CYCLE : time := 1 us;
 constant cCLR_TIME  : time := 10*cCLK_CYCLE;

 signal sCLK  : std_logic := '0';
 signal sCLR  : std_logic := '1';

 type tST is (INIT, BYTE1, BYTE0);

 signal sST  : tST       := INIT;
 signal sINI : std_logic := '0';
 signal sE   : std_logic := '0';
 signal sD   : std_logic_vector(7 downto 0) := (7 downto 0 => '0');

 signal sBYTE_CRC_oE   : std_logic;
 signal sBYTE_CRC_oD   : std_logic_vector( 7 downto 0);
 signal sBYTE_CRC_oCRC : std_logic_vector(15 downto 0);

begin

 P_sCLK : process
 begin
  sCLK <= '0'; wait for cCLK_CYCLE/2;
  sCLK <= '1'; wait for cCLK_CYCLE/2;
 end process P_sCLK;

 P_sCLR : process
 begin
  sCLR <= '1'; wait for cCLR_TIME;
  sCLR <= '0'; wait;
 end process P_sCLR;

 P_sST_sINI_sE_sD : process (sCLK)
 begin
  if (sCLK'event and sCLK = '1') then
   if (sCLR = '1') then
    sST  <= INIT;
    sINI <= '1';
    sE   <= '0';
    sD   <= (7 downto 0 => '0');
   else
    case sST is
     when INIT   =>
      sST  <= BYTE1;
      sINI <= '0';
      sE   <= '1';
      sD   <= X"6D";
     when BYTE1  =>
      sST  <= BYTE0;
      sINI <= '0';
      sE   <= '1';
      sD   <= X"27";
     when BYTE0  =>
      sST  <= BYTE0;
      sINI <= '0';
      sE   <= '0';
      sD   <= sD;
     when others =>
      sST  <= INIT;
      sINI <= '1';
      sE   <= '0';
      sD   <= (7 downto 0 => '0');
    end case;
   end if;
  end if;
 end process P_sST_sINI_sE_sD;

 U_BYTE_CRC : BYTE_CRC
 generic map (
  BPB       => 8,
  GENERATOR => cCRC_16_IBM_GENERATOR,
  ASYNC     => false
 )
 port map (
  iCLK => sCLK,
  iCLR => sCLR,
  iINI => sINI,
  iE   => sE,
  iD   => sD,
  oE   => sBYTE_CRC_oE,
  oD   => sBYTE_CRC_oD,
  oCRC => sBYTE_CRC_oCRC
 );

end architecture BENCH;

pipeline化をサボっているのでクロックが早くなるとダメになる事ウケアイ．
ま，quick'n'dirtyっつー事で． :)

MeasureSLOC(&AL9); /* 2009/03 */

AでLで9なdiffstat，3月分．
[diffstat for AL9, for 2009/03.]

 a/vhdl/BUFGMUX4_COMPAT.vhd    |  182 --------
 a/vhdl/CBUF.vhd               |  298 -------------
 a/vhdl/DCM_TROLL.vhd          |  320 --------------
 a/vhdl/FBUFG.vhd              |   91 ----
 a/vhdl/FBUFGCE.vhd            |   95 ----
 a/vhdl/LDPCD-dummy.vhd        |  116 -----
 a/vhdl/LLR2SCB.vhd            |  187 --------
 b/bench/BENCH_BER_IF_REG.vhd  |  134 ++++++
 b/bench/BENCH_SCB2SCN2SCW.vhd |  208 +++++++++
 b/bench/BENCH_TSR_CLK.vhd     |   63 ++
 b/bench/BENCH_WSX_LFSR.vhd    |  155 +++++++
 b/vhdl/BCBOOL.vhd             |  451 ++++++++++++++++++++
 b/vhdl/BER_IF_REG.vhd         |  682 +++++++++++++++++++++++++++++++
 b/vhdl/COMMON_TYPE_PKG.vhd    |   54 ++
 b/vhdl/CSSSTM.vhd             |  262 ++++++++++++
 b/vhdl/LDPCD-stub.vhd         |  113 +++++
 b/vhdl/LDPCE-stub.vhd         |  183 ++++++++
 b/vhdl/LLR2SC.vhd             |  267 ++++++++++++
 b/vhdl/SCN.vhd                |  237 ++++++++++
 b/vhdl/SCW.vhd                |  242 +++++++++++
 b/vhdl/TEIADD.vhd             |  190 ++++++++
 b/vhdl/TSR_CLK.vhd            |  475 +++++++++++++++++++++
 b/vhdl/WSX_LFSR.vhd           |  408 ++++++++++++++++++
 bench/BENCH_BER_IF_CLK.vhd    |    8 
 bench/BENCH_FCO.vhd           |   61 +-
 vhdl/BCMUX.vhd                |  149 ++++--
 vhdl/BER_IF_CLK.vhd           |    8 
 vhdl/BYTEREV.vhd              |   37 +
 vhdl/CLDPCDOP.vhd             |   83 +--
 vhdl/ELDPCDII.vhd             |   43 -
 vhdl/FCO.vhd                  |  157 ++-----
 vhdl/FCOD.vhd                 |  329 +++++++--------
 vhdl/HD2BO.vhd                |  219 +++++-----
 vhdl/LDPCD.vhd                |   59 +-
 vhdl/LDPCE.vhd                |   79 ---
 vhdl/LDPCEDB.vhd              |  914 +++++++++++++++++-------------------------
 vhdl/NIBBLESW.vhd             |   37 +
 vhdl/PN_NEGOTIATE.vhd         |   14 
 vhdl/S2BER_IF.vhd             |  278 ++++++++----
 vhdl/SBSSBDD.vhd              |  124 ++++-
 vhdl/SCB.vhd                  |  217 ++-------
 vhdl/SELDPCDIIM.vhd           |   16 
 vhdl/VTQUEUE.vhd              |  103 ++--
 43 files changed, 5554 insertions(+), 2794 deletions(-)

10kSLOC逝ってないYO!!1 :DDD
[ZOMG, under 10kSLOC!!1 :DDD]

ファイル名で分かるがLDPC関係なので，勉強ついでにコレを買ってチョロチョロ読んでいる．Reed-Solomon, Turbo, LDPCが一通り載ってるし，分厚くてとても良さ気． :)
[Yup, it's LDPC related project, so I bought this book. It explains Reed-Solomon, Turbo and LDPC. AND THEN ITZ T3H THICK!!1 :)]

Ypsilon.Makefile.karma--;

Ypsilon，R^6RSなscheme，GCがアレでメニィコアによろしいらしい．
Makefileより，

#   Makefile for Linux, FreeBSD, OpenBSD, and Darwin
#   Requirements: GNU Make, GCC 4.0 or later
#   Options: DESTDIR, PREFIX, DATAMODEL(ILP32/LP64), USE_SDL(ON)

PROG   = ypsilon

PREFIX   = /usr/local

CPPFLAGS = -DNDEBUG -DSYSTEM_SHARE_PATH='"$(DESTDIR)$(PREFIX)/share/$(PROG)"'

CXXFLAGS = -pipe -x c++ -O3 -fstrict-aliasing -fomit-frame-pointer -momit-leaf-frame-pointer

SRCS   = file.cpp main.cpp vm0.cpp object_heap_compact.cpp subr_flonum.cpp vm1.cpp object_set.cpp \
    subr_hash.cpp vm2.cpp object_slab.cpp subr_list.cpp interpreter.cpp serialize.cpp \
           vm3.cpp port.cpp subr_others.cpp arith.cpp printer.cpp subr_port.cpp subr_r5rs_arith.cpp \
    equiv.cpp reader.cpp ffi.cpp subr_base.cpp bag.cpp \
           subr_unicode.cpp hash.cpp subr_base_arith.cpp ucs4.cpp ioerror.cpp subr_bitwise.cpp utf8.cpp \
    main.cpp subr_bvector.cpp violation.cpp object_factory.cpp \
           subr_ffi.cpp object_heap.cpp subr_fixnum.cpp bit.cpp list.cpp fasl.cpp socket.cpp subr_socket.cpp

VPATH   = src

UNAME   = $(shell uname -a)

ifndef DATAMODEL
  ifeq ($(shell echo | $(CXX) -E -dM - | grep '__LP64__'), )
    DATAMODEL = ILP32
  else
    DATAMODEL = LP64
  endif
endif

ifneq (, $(findstring Linux, $(UNAME)))
  ifeq ($(shell $(CXX) -dumpspecs | grep 'march=native'), )
    ifeq ($(DATAMODEL), ILP32)  
      CXXFLAGS += -march=i686
    endif
  else
    CXXFLAGS += -march=native
  endif
  ifeq ($(shell grep -i sse2 /proc/cpuinfo), )
    CXXFLAGS += -msse
  else
    CXXFLAGS += -msse2
  endif
  CXXFLAGS += -mfpmath=sse -pthread
  ifeq ($(DATAMODEL), ILP32)  
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=32
    CXXFLAGS += -m32
    LDFLAGS = -m32
    ASFLAGS = --32
    SRCS += ffi_stub_linux.s
  else
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=64
    CXXFLAGS += -m64
    LDFLAGS = -m64
    ASFLAGS = --64
    SRCS += ffi_stub_linux64.s
  endif
  LDLIBS = -lpthread -ldl
endif

ifneq (, $(findstring FreeBSD, $(UNAME)))
  ifeq ($(shell $(CXX) -dumpspecs | grep 'march=native'), )
    ifeq ($(DATAMODEL), ILP32)  
      CXXFLAGS += -march=i686
    endif
  else
    CXXFLAGS += -march=native
  endif
  ifeq ($(shell dmesg | grep -i sse2), )
    CXXFLAGS += -msse
  else
    CXXFLAGS += -msse2
  endif
  CXXFLAGS += -mfpmath=sse -pthread
  CPPFLAGS += -D__LITTLE_ENDIAN__
  ifeq ($(DATAMODEL), ILP32)  
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=32
    CXXFLAGS += -m32
    LDFLAGS = -m32
    ASFLAGS = --32
    SRCS += ffi_stub_freebsd.s
  else
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=64
    CXXFLAGS += -m64
    LDFLAGS = -m64
    ASFLAGS = --64
    SRCS += ffi_stub_freebsd64.s
  endif
  LDLIBS = -pthread
endif

ifneq (, $(findstring OpenBSD, $(UNAME)))
  ifeq ($(shell $(CXX) -dumpspecs | grep 'march=native'), )
    ifeq ($(DATAMODEL), ILP32)  
      CXXFLAGS += -march=i686
    endif
  else
    CXXFLAGS += -march=native
  endif
  ifeq ($(shell dmesg | grep -i sse2), )
    CXXFLAGS += -msse
  else
    CXXFLAGS += -msse2
  endif
  CXXFLAGS += -mfpmath=sse -pthread
  CPPFLAGS += -D__LITTLE_ENDIAN__ -DNO_TLS
  ifeq ($(DATAMODEL), ILP32)  
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=32
    CXXFLAGS += -m32
    LDFLAGS = -m32
    ASFLAGS = --32
    SRCS += ffi_stub_openbsd.s
  else
    CPPFLAGS += -DDEFAULT_HEAP_LIMIT=64
    CXXFLAGS += -m64
    LDFLAGS = -m64
    ASFLAGS = --64
    SRCS += ffi_stub_openbsd64.s
  endif
  LDLIBS = -pthread
endif

ifneq (, $(findstring Darwin, $(UNAME)))
  CXXFLAGS += -arch i386 -msse2 -mfpmath=sse
  CPPFLAGS += -DNO_TLS
  SRCS += ffi_stub_darwin.s
  ifneq (, $(USE_SDL))
    CPPFLAGS += -DUSE_SDL
    LDFLAGS = extension/SDL/darwin/i386/SDLmain.o -framework SDL -framework Cocoa 
  endif
endif

[SNIP]

clean:
 rm -f *.o *.d
 rm -f $(HOME)/.ypsilon/*.cache 
 rm -f $(HOME)/.ypsilon/*.time

[SNIP]

x86/amd64大好きらしい，cleanは$(HOME)までお掃除する親切設計． :DDD

NetSurf / FrameBuffer #2

今日もframe buffer portをモニョった．

FTC_CMapCache_Lookup()でsegvるのは，error handlingがタコだったのとフォントへのパスがhardcodedで間違ってたのが原因．で，まずはSDL+freetype on Xで動くようになった．


さすがに黄色過ぎるので，internal pixel-colour変換を直すと，テキストの色は正しくなった．



endian dependな部分は泥臭くもあり，面白くもある．変な風にinternal pixel-colour変換がぶっ壊れると色がぶっ飛ぶ． :DDD

 02/28 01:24:33 hiyuh
    any idea? http://dev.gentoo.gr.jp/~hiyuh/misc/BE2.patch
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-BE2.png
 02/28 01:25:15 hiyuh
    it looks like only image ablend is broken, I guess.
 02/28 01:25:54 Kinnison
    looks like that
 02/28 01:26:13 kyllikki
    blue and green traded in your pixel to colour
 02/28 01:32:15 hiyuh
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-BE2-web-colors.png
 02/28 01:32:35 hiyuh
    text color is correct?
 02/28 01:33:03 kyllikki
    yes
 02/28 01:33:29 kyllikki
    the alpha blending is broken because the values its reading in to
    mix are wrong
 02/28 01:34:23 tlsa
    opaque images are wrong too
 02/28 01:34:33 hiyuh
    wtf :)
 02/28 01:34:57 tlsa
    well the screenshot is opaque, so is the logo image
 02/28 01:35:20 kyllikki
    I have no idea then
 02/28 01:35:38 kyllikki
    maybe the image formatters are getting it wrong on big endian systems?
 02/28 01:35:58 tlsa
    they'd be bust when he runs nsgtk
 02/28 01:38:40 hiyuh
    nsgtk works correctly on BE.
 02/28 01:40:11 tlsa
    there's something more wrong than just channel swapping
 02/28 01:40:36 tlsa
    cos the logo in the download box and the logo in the mast head should
    be the same colour
 02/28 01:40:46 tlsa
    but they are completely different
 02/28 01:45:01 tlsa
    actually, that's cos the background is different and the images are
    incorrectly getting alpha values other than opaque
 02/28 01:47:36 tlsa
    does the gtk build swap bitmap data round on BE?
 02/28 01:49:11 tlsa
    cos it looks perfect except for bitmaps
 02/28 01:54:21 hiyuh
    IIRC, nsgtk's image problems on BE was only in libnsgif code base
    (maybe it was in netsurf/image/gifread.c).
 02/28 01:56:37 tlsa
    well there's something certainly wrong with images
 02/28 01:56:50 tlsa
    and nothing wrong with text colours
 02/28 01:57:20 hiyuh
    true

と言う訳で，もう少しゴニョる必要があるのだったのだった． :)

NetSurf / FrameBuffer

#netsurfがframbuffer portで盛り上がっていたので，モニョる． :DDD

 02/26 21:01:19 hiyuh
    what does NETSURF_FB_FRONTEND=able mean?
 02/26 21:01:50 hiyuh
    runtime linux/sdl detection?
 02/26 21:02:29 tlsa
    to pick whether to build nsfb for the linux, able or other framebuffer
 02/26 21:02:54 kyllikki
    the list is now able, sdl, linux and vnc
 02/26 21:03:16 kyllikki
    sdl, linux and vnc are mostly what you will be interested in

 02/26 21:24:47 hiyuh
    nsfb-{sdl,linux} doesn't work here. :(
 02/26 21:26:09 rjek
    You won't get much help without details :)
 02/26 21:26:54 hiyuh
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-linux-r6625-fsckedup.jpg

 02/26 21:27:11 hiyuh
    color is fscked up completely. :)
 02/26 21:27:22 rjek
    Oh, an endianess problem.
 02/26 21:27:30 rjek
    TTOTD: Don't use big-endian machines.
 02/26 21:27:33 rjek
    :)
 02/26 21:28:09 hiyuh
    keyboard/mouse doesn't work too, so I did force powerdown this
    powerbook. :DDD
 02/26 21:29:22 hiyuh
    tested only x86 boxes?
 02/26 21:29:27 rjek
    And ARM.
 02/26 21:29:33 rjek
    Extensively on ARM, in fact.
 02/26 21:29:39 hiyuh
    ah, k
 02/26 21:31:10 jmb
    awesome
 02/26 21:31:17 jmb
    kyllikki: that rocks
 02/26 21:41:02 jmb
    hiyuh: I assume keyboard/mouse work correctly under sdl?
 02/26 21:43:45 jmb
    as for endianness, it's likely in the plotters
 02/26 21:45:18 hiyuh
    jmb: sadly, nope. sdl's one said "Unable to init SDL: Unable to open
    mouse" then segv immediately (was tested on X/fbconsole).
 02/26 21:45:29 jmb
    hiyuh: oddness
 02/26 21:46:59 jmb
    hiyuh: I assume other SDL apps work?
 02/26 21:47:16 hiyuh
    jmb: let me check
 02/26 21:47:51 jmb
    hiyuh: because the SDL_Init() call we have is entirely standard :)
 02/26 21:51:09 hiyuh
    jmb: it works on X, but it doesn't work on fb. maybe, causes of
    "sdl's ones didn't work on X/fbconsole" are different.
 02/26 21:52:13 jmb
    hiyuh: right
 02/26 21:57:48 hiyuh
    jmb: I guess X blocks mouse device access from SDL when I was on
    fbconsole, I'll check w/o running X (no VT switch).
 02/26 21:57:50 jmb
    there. updated the application
 02/26 21:58:02 jmb
    hiyuh: wouldn't surprise me
 02/26 21:58:09 hiyuh
    yup, bbl

 02/27 00:17:11 hiyuh
    jmb: cause of SDL_init error comes from my udev rules were
    fscked up, sorry. even though, sdl's one still rocks. :)
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-sdl-r6625-fsckedup-270.jpg

 02/27 00:18:34 Kinnison
    hiyuh: are colours in web pages wrong too?
 02/27 00:18:40 Kinnison
    Or just the furniture?
 02/27 00:21:05 hiyuh
    nope, it can not show any page ATM.
 02/27 00:21:51 Kinnison
    Odd
 02/27 00:21:56 Kinnison
    why not?
 02/27 00:23:24 tlsa
    Kinnison: web page colours were wrong in is photo:
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-linux-r6625-fsckedup.jpg
 02/27 00:27:06 Kinnison
    hmm
 02/27 00:27:39 Kinnison
    presumably this is kyllikki needing to support endianness stuff in
    his plotters?
 02/27 00:28:54 hiyuh
    fb_plotters_ablend()?
 02/27 00:30:37 Kinnison
    that's the alphablend isn't it?
 02/27 00:31:16 hiyuh
    I guess. it calculates r/g/b.
 02/27 00:50:09 kyllikki
    hi
 02/27 00:50:14 tlsa
    re k
 02/27 00:50:59 kyllikki
    right for big endien the least invasive way is to have different
    plotter c files built
 02/27 00:51:44 kyllikki
    e.g. fb_32bpp_plotters_be.c
 02/27 00:52:14 kyllikki
    because although the machines words are BE it appears the framebuffer
    display is LE
 02/27 00:52:39 kyllikki
    I suppose I could make it generic but...
 02/27 00:52:44 rjek
    How much of the code is actually different?
 02/27 00:52:47 rjek
    Might #ifdefing be better?
 02/27 00:53:08 kyllikki
    rjek: I really didnt want a load more #ifdeffery
 02/27 00:53:20 rjek
    Well, if large bits of the function will be different, I agree.
 02/27 00:53:30 kyllikki
    I am thinking of ways to remove the existing ifdefery
 02/27 00:53:52 kyllikki
    rjek: its every time an output colour is computed
 02/27 00:54:04 kyllikki
    so its not everso often
 02/27 00:57:04 kyllikki
    no, i see it
 02/27 00:57:08 kyllikki
    I can generalise it
 02/27 00:57:24 kyllikki
    in fact i ought to
 02/27 01:02:11 tlsa
    is it easy to add the rest of those pointers?
 02/27 01:06:42 kyllikki
    what #define can i use to determine endiness at compile time?
 02/27 01:09:55 hiyuh
    ? http://dev.gentoo.gr.jp/~hiyuh/misc/netsurf-gifread-try2fixonBE.diff
 02/27 01:11:02 kyllikki
    cool
 02/27 01:14:53 kyllikki
    try that?
 02/27 01:15:04 kyllikki
    I *think* my shifts are right
 02/27 01:15:50 kyllikki
    you get to test if #if __BYTE_ORDER == __BIG_ENDIAN is right
 02/27 01:16:45 hiyuh
    ACK
 02/27 01:19:38 *
    kyllikki waits paitently

 02/27 01:29:08 hiyuh
    lol
 02/27 01:29:09 hiyuh
    http://dev.gentoo.gr.jp/~hiyuh/misc/nsfb-sdl-r6635-onX-fsckedup.jpg

 02/27 01:29:46 hiyuh
    mouse/keyboard works. :)
 02/27 01:29:49 kyllikki
    hmm thats 32bpp?
 02/27 01:30:12 hiyuh
    dunno, just run nsfb on X.
 02/27 01:30:23 kyllikki
    well 32bpp is the default
 02/27 01:32:49 hiyuh
    let me try -linux.

 02/27 03:39:52 hiyuh
    on 32bpp nvidiafb, -linux shows red screen, keyboard/mouse doesn't
    work and cpu usage goes 100%  then I did force poweroff.
 02/27 03:40:01 hiyuh
    FYI, generic ppc machine uses offb which is 8bpp by default.
 02/27 03:40:05 hiyuh
    kyllikki: ^^
 02/27 03:40:39 kyllikki
    right, the 8bpp plotters may indeed be funted
 02/27 03:41:07 kyllikki
    hiyuh: I will take a look, maybe later maybe morrow
 02/27 03:41:15 kyllikki
    tired atm
 02/27 03:41:20 hiyuh
    k, thx
 02/27 03:41:24 kyllikki
    np

つーわけで，次回に持ち越し．
今のところ，一番まともなのは-sdlを32bpp nvidiafbで動かす場合かな．
nouveauの中の人は{nvidia,riva}fbはstateがゴチャゴチャになるからofonlyにしろって言うし，offbは32bppにならねーし，どーすっか．


で，NETSURF_FB_FONTLIB=freetypeにしたら，FTC_CMapCache_Lookup()でSEGVるのを発見．
gcc-4.3.3のbugかもしれんので，熟成の方向で． :P

tanslate(mercurial_ref, "ja_JP.UTF-8");

例のAでLな"ぷろじぇくつ"の残務も一段落したし，matsuu先生がブツの日本語訳を御所望なのでモニョる．
PowerBookにmedia-gfx/inkscapeをemergeするのはgnome depでコンパイルがダルいので，会社のパソコンにWindows版のinkscapeをぶち込んで仕事をしているフリをする． :DDD

で，出来たので晒す．


もっと大きいのが欲しいひとはこことここにあるので，御自由にどうぞ．
SVGはここに突っ込んだ．訳がヘチョいのとフォントがMS-Gothicになってるのが御愛嬌と言うことで． :P

emerge nouveau

AでLな"ぷろじぇくつ"に20kLOC overのVHDLを書きまくって，なんとか終わったのでnouveauで遊ぶ．

一応，upstream(?)のもあるにはあるが頑なにGallium3D対応にしようとしないので，今までmedia-libs/mesaだけ野良buildしていたがebuildにしてみた．proj/x11.gitとかからlive ebuildをパクってきて，モニョる． :DDD

まだTTMがアレなので，アレだのう． :S

if (!open("/dev/code", O_RDONLY)) { ...; }

NWCCの中の人とのメールの一部．

俺の好きなマイナーなブツに限らず，dev codeを拝めないことは良くある．メジャー/マイナーに関わらず，dev codeは爆弾な訳で，だからこそ見る側からすれば面白かったりするのだが，出す方は迷いもある．作り手である分，被害が具体的に予想出来てしまうのが原因，多分．

DSCMで気軽にブツを晒せる昨今になっても，changesetを綺麗にしてから出直して来いとか言ってrejectするメジャードコロでもあるまいし，自家製爆弾くらいを公開したって別に良くね？一つや二つ程度の地雷を踏んだ程度でupstreamの追っかけを止めるくらいなら，最初っから追っかけなんかやってんな，と．LICENSEは読んだか？ちゃんと，「爆発しても知らねーからな！！1」って書いてあるよ，だいたい．爆弾だったとき文句を言われのが嫌？別に爆弾じゃなくても文句なんていつも言うだろ，実際． :DDD

Rakuten.karma++;

なんやかんやでmatsuu尊師がアレでナニすることになったので、ひきこもらずに楽天テクノロジーカンファレンス2008に行ってきた。駅から会場まですーぱー迷いつつ華麗に遅刻。会場ではスーツ着込んだ楽天の中の人（？）がそこら中にいて、「いらっしゃいませ」とかしてた。プチ引きこもりなので素でキョドる。もっとイイ加減でいいと思うんだがなー、とも思うが、それっぽいと言えばそれっぽい。

オープニングのRubyのエラい人は何かありがたい事を言ってた、多分。 :P
ディストリビューション大集合はmatsuu尊師がKYじゃなかった、残念。 :P
昼飯喰ってなかったので、ジャスコでパン買って喰って帰ってきたら、debianの中の人（？）がIPAを再びdisってた。イイね、もっとやれ。燃えろ、flameだ、pop corn timeだ。 :DDD
クロージングは楽天のエラい人が何かそれっぽい事を言ってた、とても良いサクラでした。 :P
噂に聞くタダメシはとてもおいしゅうござました、ゴチ。 :9

インクリメントしたのが、なんのkarmaなのかは想像にお任せします。 :)

帰ってから、よしおかさんのblogとかをほげほげ。

以下、勉強会について思うどうでもいいこと。

今年度、なぜか会社で勉強会の真似事の様な事を一週間に一回してたりする。お題は日本語訳されたK&R Cと言うありがたーい経典の輪読。仕事でCのコードを書いている人なら読んでいなければモグリなんだろうけど、それはそれ。俺としては、もう少しacademicな英語の論文とか大学/大学院レベルの教科書とか標準規格書とかLRMとかを使いたいと思ってたんだけど、「誰も分からんだろうが、バカモノ」みたいな事をボスに言われたので、幾つか私物の日本語で書かれた本を持っていったら、何となくそう言う事になった。

で、時間は午後六時くらいから一時間ほど。パラグラフ単位程度を輪読して、適宜、俺がどーでもよろしい薀蓄を垂れたり垂れなかったりすると言うなんともやる気の無い進行。例の如く進みがカメなので、今もポインタの辺りをムニャムニャ中なりよ。更に、年度末が近づくに従ってプロジェクトが佳境になっていくのか、当初の誰かの予想通りと言うか何というか、参加者はみるみる減っていき、今は不良講師（？）の俺と同期の子一人だけと言う体たらく。

たまーに、「もう止めようか？」と俺から言うのだけれど、その子曰く、続けたいらしいのでまだ二人でダラダラやっている。「その時間は仕事をしないでオタクの話を聴いている振りをすれば楽だから」と言う考えが邪推が出来ない訳でもないが、他人の本音は訊いても分からんのでその辺りはどうでもよろしいと割り切っている、つもり。まー、大抵のオタクはその手のアレな事をテキトーに喋るのが好きだし、それを聴いている相手が理解していようといまいとあんまり関係なかったりするからね。テキトーに相槌さえしてれば、殆どのオタクには見分けなんかつかないよ。だって私生活でフツーの人となんか殆ど話なんかしないからな。そんな感じで「別に相手が理解なんかしてなくても、どーでもよろしい」なんて思っていると言うイイ加減なヤツがいたりするので、更にフツーの人の手には負えなかったりするんだろうけど、残念ながら例に漏れず俺もそうなので。んー、改めて言葉にしてみると、ホントにどーしよーもないな、コレは。 :DDD

規模やら参加する対象、勉強する内容を問わず、自主的な勉強会についてって話になると、俺自身の経験だと高専時代にもやってたりする。当時、蝶生意気な事で先輩から非常に高得点の悪評を頂いていた高専生だった俺は、何を血迷ったのか、担任の先生に「土曜日に線形代数を教えてくれ」なんてアホな事を言った。確か、何年か上の先輩が「Harword Antonの線形代数の本はmust readだ」みたいな事を喋っていた時に隣に座っていた影響だと思う。

殆どの工学系の学問はベクトルやら行列やらの演算が基礎にあるので、必然的に基礎科目として線形代数ってのはどこでもやっているのだけれど、ここで言う線形代数ってのは、高専三年から高専五年や学部一年から学部二年の奴等が勉強している線形代数とは別chapter的な線形代数、要は線形空間以降の話ね。

同級生とか留学生とか卒業研究中の先輩とかも参加してて、週休二日制になって殆ど誰も居ない学校に土曜日の朝十時くらいから来て昼までムニョムニョ。当時の俺は一通り教えて貰ってから、「目から鱗が落ちた」とか夜まで騒いでいて、その先生に会うと何時もネタにされるけれど、まー、若気の至りですよ、勘弁勘弁。それから続きでepsilon-deltaとかもやってもらった、感謝感謝。で、つい最近、実家に帰省する機会があって、その先生に会いに行ったら、今も現役の学生を捕まえて勉強会をしていて、その時間にお邪魔してテキトーに「ほーほー」とか言いながら授業参観（？）してきた。

ま、あれですよ。勉強会なんてテキトーにやればいいんじゃないですかね、テキトーに。内輪ネタで盛り上がっている感はあるけど、そーゆーのに参加している一人としても、あんまり使命感も危機感も無い。ただ、何となく似たようなオタクっぽい人種の集まりで発表を私語まじりで訊いたり、モノ喰いながら時々脱線した話をしたりするのが中毒になっているだけだなー、少なくとも俺は。

知識や情報云々を比べ始めると上も下もキリなんか無い。実際になんか使って比べたり、仕事とかの中で明らかな差が出てきた時には「もう手の施しようがありません」みたいな。でも、そーゆー事態にならんとフツーの人は危機感なんか持たんでしょ、多分。主催する側に何時の間にか回ってしまった人達がその辺りのギャップやら埋めようと頑張っているのはとてもありがたいことですが。前に「フツーのひとは仕事が終わったら家ではPCなんかさわらないし、休みの日は仕事の事なんか考えたくもないって思ってると思え」って言われた事があって、「あらあら、まぁまぁ」なんて思ったけど、そーゆーモノかと納得出来てしまうあたりそーゆーモノなんでしょうよ、少なくとも今は。そーゆーヤツラは「もう手の施しようがありません」ですよ、はい。「そーゆー事なら相手するのもメンドイと思っている」と言う所では俺の方が終わっているかもしれないが。 :DDD

あー、そうそう。それと勉強会についての話ついでなんだが、"プログラマ"とか一括りしたり分類したりすんの、ダメ、絶対。レイヤには上も下もキリなんかないからね。Web 2.0とかBinary 2.0とか、高位言語やらアセンブラを理解しているいないとか、OSがどーとか、コンパイラがこーとか、デバドラは云々とか言うけど、私事ですがハード屋の中にも俺みたいなオタクが混じっている時代です。あんたらが使っている無線LANカードのchipは俺がその1 bit、1 clockに至るまでテキトーに設計したモノが元になっているかもしれませんよ。 :P

そして俺がでしゃばれば、半導体物性の人が俺をdisるでしょう。その人は量子力学の学者にdisられる可能性があります。で、その人は数学の学者にdisられるかもしれません。そして、フツーの人たちは俺たちを「そんな熱くなるなよ、やっぱりオタクはわけわかんねぇ」と言うのです、きっと。 :DDD

# 英語ダルい。 :P

stack(TODO);

TODO、めもめも。 :)
MOLのsvn trunkをムニャる。
GRUB2のsvn headをムニャる。
waylandのgit masterをムニャる。

IsScheme(&code) || IsC(&code)

sibling callsに拘りすぎて、parserあたりからC言語とは思えない件について。
[It's crazy sibling calls hand-optimization, so doesn't looks like C language code anymore.]
grmpp.c
どうみてもschemeの影響です、ほんとうにありがとうございました（ぼーよみ。 :DDD
[Well, inspired by scheme, KTHXBYE. :DDD]

I CAN HAS VHDL? #4

VHDLについて、テキトーに書いてみるべす、第四回。

前回はロードとイネーブル付きの蝶テキトーなカウンタしかださなかったので、少しマトモなモノにしてみる。"すとりーむ"な信号処理をメインにメシを喰っているので、その辺りから。比較的簡単なブツで、しかもVHDLっぽいモノっつー訳で移動平均フィルタにしますか。

はい、まずは数学的基礎。離散時間表現では、
\overline{x[k + L]} = 1/N \sum_{n = 0}^{N} x[k - n]
ですな。移動平均長がNで実装上のレイテンシーがLね。そんだけ。

じゃあ、実装です。とりあえず、こうしようぜ。
\overline{x[k + L]} = (x[k] + x[k-1] + ... + x[k - N]) / N
完璧ですね、と思ったアナタには漏れ無くパンチをプレゼント。 :DDD

次の様に漸化式にするのが、王道です。
\delta S[k + L_1] = x[k] - x[k - L]
S[k + L_2] = S[k] + \delta S[k]
\overline{x[k + L_3]} = S[k] / N
さらに実装を容易にする為、Nを2の冪乗に限定する事で除算を算術右シフトにします。
\delta S[k + L_1] = x[k] - x[k - N]
S[k + L_2] = S[k] + \delta S[k]
\overline{x[k + L_3]} = SAR(S[k], log_{2}(N))
つまり、移動平均長Nだけ離れた入力の差分を積算してテキトーに上位ビットを切り出すだけと言う簡単な回路。

あまりに簡単過ぎるので、もう少し内容を盛り込む。
まずは、instantiateする場合にcomponent declarationを書くのがダルいのでpackageを作って、use clauseを使う。つぎに、architecture bodyで使うsignalをrecordを使ってムニゃる。あと、synchronous/asynchronous resetに対応する。

以下、ソース。

     1 --
     2 -- Moving Average Filter
     3 --
     4 
     5 library ieee;
     6 use ieee.std_logic_1164.all;
     7 
     8 package MAF_PKG is
     9 
    10     component MAF is
    11         generic (
    12             IS_SYNC : boolean                         := true;
    13             DW      : integer range 2 to integer'high :=   12;
    14             log2N   : integer range 1 to integer'high :=    3
    15         );
    16         port (
    17             iCLK : in  std_logic;
    18             iCLR : in  std_logic;
    19             iD   : in  std_logic_vector(DW-1 downto 0);
    20             oQ   : out std_logic_vector(DW-1 downto 0)
    21         );
    22     end component MAF;
    23 
    24 end package MAF_PKG;
    25 
    26 package body MAF_PKG is
    27 
    28 end package body MAF_PKG;
    29 
    30 library ieee;
    31 use ieee.std_logic_1164.all;
    32 use ieee.std_logic_arith.all;
    33 
    34 entity MAF is
    35     generic (
    36         IS_SYNC : boolean                         := true;
    37         DW      : integer range 2 to integer'high :=   12;
    38         log2N   : integer range 1 to integer'high :=    3
    39     );
    40     port (
    41         iCLK : in  std_logic;
    42         iCLR : in  std_logic;
    43         iD   : in  std_logic_vector(DW-1 downto 0);
    44         oQ   : out std_logic_vector(DW-1 downto 0)
    45     );
    46 begin
    47 end entity MAF;
    48 
    49 architecture TP of MAF is
    50 
    51     constant cN : integer range 2 to integer'high := 2**log2N+1;
    52 
    53     type tD is array (0 to cN-1) of std_logic_vector(DW-1 downto 0);
    54     type t  is record
    55         D   : tD;
    56         dS  : std_logic_vector(      DW   downto 0);
    57         dSE : std_logic_vector(log2N+DW-1 downto 0);
    58         S   : std_logic_vector(log2N+DW-1 downto 0);
    59         Q   : std_logic_vector(      DW-1 downto 0);
    60     end record t;
    61 
    62     constant c : t := (
    63         D   => (others => (others => '0')),
    64         dS  => (others => '0'),
    65         dSE => (others => '0'),
    66         S   => (others => '0'),
    67         Q   => (others => '0')
    68     );
    69 
    70     signal g : t;
    71     signal r : t := c;
    72 
    73 begin
    74 
    75     P_COMB : process (iD, r)
    76         variable v : t;
    77     begin
    78         -- NOTE: Shift inputted data (D).
    79         F_SHIFT_D : for index in 0 to cN-1 loop
    80             if (index = 0) then
    81                 v.D(index) := iD;
    82             else
    83                 v.D(index) := r.D(index-1);
    84             end if;
    85         end loop F_SHIFT_D;
    86 
    87         -- NOTE: Compute delta sum (dS).
    88         v.dS :=
    89             signed(r.D(   0)(DW-1) & r.D(   0)) -
    90             signed(r.D(cN-1)(DW-1) & r.D(cN-1));
    91 
    92         -- NOTE: Sign expansion for delta sum (dSE).
    93         v.dSE(log2N+DW-1 downto DW) :=     (log2N  -1 downto 0 => r.dS(DW));
    94         v.dSE(      DW-1 downto  0) := r.dS(     DW-1 downto 0);
    95 
    96         -- NOTE: Accumulate sum (S).
    97         v.S := signed(r.S) + signed(r.dSE);
    98 
    99         -- NOTE: Divide sum by length for MA (Q).
   100         v.Q := r.S(log2N+DW-1 downto log2N);
   101 
   102         g  <= v;
   103         oQ <= r.Q;
   104     end process P_COMB;
   105 
   106     G_SYNC : if (IS_SYNC = true) generate
   107     begin
   108         P_SEQ : process (iCLK)
   109         begin
   110             if (iCLK'event and iCLK = '1') then
   111                 if (iCLR = '1') then
   112                     r <= c;
   113                 else
   114                     r <= g;
   115                 end if;
   116             end if;
   117         end process P_SEQ;
   118     end generate G_SYNC;
   119 
   120     G_ASYNC : if (IS_SYNC = false) generate
   121     begin
   122         P_SEQ : process (iCLR, iCLK)
   123         begin
   124             if (iCLR = '1') then
   125                 r <= c;
   126             elsif (iCLK'event and iCLK = '1') then
   127                 r <= g;
   128             end if;
   129         end process P_SEQ;
   130     end generate G_ASYNC;
   131 
   132 end architecture TP;

はい、簡単ですね。 :)

さらに、何時もの様にやる気の無いテストベンチを作る。

     1 library ieee;
     2 use ieee.std_logic_1164.all;
     3 use ieee.std_logic_arith.all;
     4 use work.MAF_PKG.all;
     5 
     6 entity BENCH_MAF is
     7 begin
     8 end entity BENCH_MAF;
     9 
    10 architecture BENCH of BENCH_MAF is
    11 
    12     constant cIS_SYNC : boolean                         := true;
    13     constant cDW      : integer range 2 to integer'high :=   12;
    14     constant clog2N   : integer range 1 to integer'high :=    5;
    15     constant cN       : integer range 2 to integer'high := 2**clog2N;
    16 
    17     constant cCLK_CYCLE : time := 1.0 us;
    18     constant cCLR_TIME  : time := (cN+1)*cCLK_CYCLE;
    19 
    20     signal sCLK             : std_logic := '0';
    21     signal sCLR             : std_logic := '1';
    22     signal sLFSR_D          : std_logic_vector(cDW-1 downto 0) := (others => '0');
    23     signal sTRIANGLE_D      : std_logic_vector(cDW-1 downto 0) := (others => '0');
    24     signal sMAF_LFSR_oQ     : std_logic_vector(cDW-1 downto 0);
    25     signal sMAF_TRIANGLE_oQ : std_logic_vector(cDW-1 downto 0);
    26 
    27     function fLFSR (
    28         iD  : std_logic_vector;
    29         iDW : integer range 2 to integer'high
    30     ) return std_logic_vector is
    31     begin
    32         if (iDW = 12) then
    33             return (iD(7) xor iD(4) xor iD(3) xor iD(0)) & iD(11 downto 1);
    34         else
    35             assert (iDW = 12)
    36                 report "fLFSR: Call with non-supported iDW!!1" -- :P
    37                 severity warning;
    38             return iD;
    39         end if;
    40     end function fLFSR;
    41 
    42     function fTRIANGLE (
    43         iD  : std_logic_vector;
    44         iDW : integer range 2 to integer'high
    45     ) return std_logic_vector is
    46     begin
    47         if (signed(iD) <= -2**(iDW-1)) then
    48             return conv_std_logic_vector(2**(iDW-1)-2**6, iDW);
    49         else
    50             return signed(iD) - 2**6;
    51         end if;
    52     end function fTRIANGLE;
    53 
    54 begin
    55 
    56     P_sCLK : process
    57     begin
    58         sCLK <= '0'; wait for cCLK_CYCLE/2;
    59         sCLK <= '1'; wait for cCLK_CYCLE/2;
    60     end process P_sCLK;
    61 
    62     P_sCLR : process
    63     begin
    64         sCLR <= '1'; wait for cCLR_TIME;
    65         sCLR <= '0'; wait;
    66     end process P_sCLR;
    67 
    68     P_sD : process (sCLK)
    69     begin
    70         if (sCLK'event and sCLK = '1') then
    71             if (sCLR = '1') then
    72                 sLFSR_D     <= (others => '1');
    73                 sTRIANGLE_D <= (others => '0');
    74             else
    75                 sLFSR_D     <= fLFSR(sLFSR_D, cDW);
    76                 sTRIANGLE_D <= fTRIANGLE(sTRIANGLE_D, cDW);
    77             end if;
    78         end if;
    79     end process P_sD;
    80 
    81     U_MAF_LFSR : MAF
    82     generic map (
    83         IS_SYNC => cIS_SYNC,
    84         DW      => cDW,
    85         log2N   => clog2N
    86     )
    87     port map (
    88         iCLK => sCLK,
    89         iCLR => sCLR,
    90         iD   => sLFSR_D,
    91         oQ   => sMAF_LFSR_oQ
    92     );
    93 
    94     U_MAF_TRIANGLE : MAF
    95     generic map (
    96         IS_SYNC => cIS_SYNC,
    97         DW      => cDW,
    98         log2N   => clog2N
    99     )
   100     port map (
   101         iCLK => sCLK,
   102         iCLR => sCLR,
   103         iD   => sTRIANGLE_D,
   104         oQ   => sMAF_TRIANGLE_oQ
   105     );
   106 
   107 end architecture BENCH;

見ての通り、入力はLFSRとノコギリ波。

前者をMAF.vhdl、後者をBENCH_MAF.vhdlとして、GHDLとGTKWaveでモニョる。workディレクトリを作って、analyzeして、elaborate。

$ mkdir work
$ ghdl -a --std=02 --workdir=./work --ieee=synopsys MAF.vhdl
$ ghdl -a --std=02 --workdir=./work --ieee=synopsys BENCH_MAF.vhdl
$ ghdl -e --std=02 --workdir=./work --ieee=synopsys -o BENCH_MAF-BENCH BENCH_MAF BENCH

GHWなwaveファイルを吐くオプションを付けて500[us]くらいrunさせてー、GTKWaveでモニョモニョ。

$ ./BENCH_MAF-BENCH --stop-time=500us --wave=BENCH_MAF-BENCH-500us.ghw
$ gtkwave BENCH_MAF-BENCH-500us.ghw

ハイ、いい感じに移動平均されているアルよ。 :)

以上の様に、結構いい感じのtwo-process手法だが、これ一本槍だと幾つか欠点があったりする。と言う感じで次回に続くのであったのであった。 :P

BModular(&NetSurf, 1);

GSoCな感じで盛り上がっていたNetSurfの成果を確かめる為、再びモニョる。 :)
[NetSurd upstream did merge bunch of GSoC student code into their svn trunk.
So, it's time to BUMB!!1 :)]

09/18 00:55:20 hiyuh
    hey, !NetSurf/Resources/*/Messages are used in gtk port?
09/18 00:55:38 jmb
    not at present
09/18 00:55:47 jmb
    well, s/*/en/ is
09/18 00:56:01 hiyuh
    only en for now?
09/18 00:56:04 jmb
    yeah
09/18 00:56:27 jmb
    assuming that there's some UI to select the interface language,
    and some code to determine the correct default, then they can be
09/18 00:56:55 hiyuh
    true
09/18 00:58:00 jmb
    basically, it needs someone to put in the small amount of effort
    required to make them useful :)
09/18 00:59:03 hiyuh
    I'm not gtk guy, but I can translate en to ja. :)
09/18 00:59:12 tlsa
    didn't we get a czech translation?
09/18 00:59:12 jmb
    that'd be cool
09/18 00:59:14 tlsa
    cool
09/18 00:59:39 jmb
    point being that these Messages files get used on all platforms,
    so only need translating once :)
09/18 01:00:15 tlsa
    is ja japanese?
09/18 01:00:20 tlsa
    i thought that was .jp
09/18 01:00:44 jmb
    depends which registry you're looking at :)
09/18 01:00:53 jmb
    ja is the ISO-639 2 letter language code
09/18 01:01:13 hiyuh
    anyway, I meant japanese.
09/18 01:01:21 tlsa
    ok
09/18 01:01:43 tlsa
    a Japanese translation would be great, anyway :)
09/18 01:02:36 tlsa
    hey, if you could translate http://www.netsurf-browser.org/welcome/
09/18 01:02:47 tlsa
    then I could test the language negotiation :)
09/18 01:02:55 jmb
    hee
09/18 01:03:09 tlsa
    we've only had English since the site was redesigned
09/18 01:03:21 hiyuh
    lol
09/18 01:03:27 hiyuh
    before translate en to ja, I should make modular NS ebuilds for
    gentoo, am pokin' json-c now.
09/18 01:03:47 jmb
    shouldn't need json-c at all
09/18 01:03:50 tlsa
    ok
09/18 01:04:04 jmb
    certainly not unless you actually want to do make test in hubbub
09/18 01:05:02 hiyuh
    yup, I read README, and IIRC I already told hubbub's make test hogs
    my entire mem.
09/18 01:05:30 hiyuh
    but someone needs to test. :p
09/18 01:05:37 jmb
    yes, it does
09/18 01:05:43 jmb
    I can probably lose that now, actually
09/18 01:11:36 tlsa
    hiyuh: on the welcome page, the links at the bottom can be changed
    to relevant stuff for the language
09/18 01:11:54 tlsa
    3 items in first column, which is "News"
09/18 01:12:21 tlsa
    4 items in 2nd column, which is "IT / web"
09/18 01:12:54 tlsa
    4 items in 3rd column, which is "Information"
09/18 01:13:14 tlsa
    3 items in 4th column, which is "RISC OS"
09/18 01:13:27 tlsa
    prob. not much choice for RISC OS sites though :0
09/18 01:13:38 tlsa
    s/:0/:p/
09/18 01:14:55 tlsa
    the only other guidelines are that the sites should be big and
    important in their field, and that you should not need to log in to
    use them (so no webmail sites / forums etc)
09/18 01:16:14 tlsa
    wikipedia can be easily changed to the ja one
09/18 01:16:28 tlsa
    and we should have W3C in all translations
09/18 01:18:22 jmb
    hiyuh: svn up libparserutils
09/18 01:18:31 jmb
    should stop the memory leaks :)
09/18 01:18:38 tlsa
    and if you link to pages in a different language, use "BBC News
    (English)" or the common abreviation like "BBC News (en)", except
    translated of course :)
09/18 01:19:09 hiyuh
    jmb: ok I'll try
09/18 01:22:45 hiyuh
    tlsa: translating to ja is a plan as my next todo. I'd like to check
    whether recent NS still did wrong line breaking or not, at first.
09/18 01:23:00 tlsa
    i think it does
09/18 01:23:23 tlsa
    we don't do propper unicode line breaking
09/18 01:23:29 tlsa
    at least on RISC OS
09/18 01:23:54 tlsa
    i'm not sure if that's RUfl or NetSurf's problem, on RO
09/18 01:25:16 hiyuh
    eew
09/18 01:30:01 tlsa
    gah, I can't screenshot the sonic team page
09/18 01:30:13 tlsa
    it says Parsing the document failed
09/18 01:30:19 tlsa
    jmb: is that encoding related?
09/18 01:30:46 tlsa
    ( http://www.sonicteam.com/ )
09/18 01:33:30 tlsa
    Shift_JIS
09/18 01:44:00 tlsa
    can we make the RISC OS version use the homepage in Makefile.config
    and override it on the autobuilder?
09/18 01:44:48 tlsa
    then my local checkout will be able to use that and not need to have
    my local copys which generate loads of stuff for "svn status"
09/18 02:04:53 hiyuh
    jmb: json-c is 0.3? ChangeLog has history to 0.8. and its autogen.sh
    breaks w/ latest auto*, I guess.
09/18 02:05:04 jmb
    pass
09/18 02:05:28 jmb
    I just checked out upstream's svn HEAD, then patched it
09/18 02:07:37 hiyuh
    ah, ok
09/18 02:10:46 tlsa
    http://source.netsurf-browser.org/?view=rev&revision=5367
09/18 02:12:42 tlsa
    one thing I noticed was that BeOS doesn't have a setting for Hubbub
    (has it been ported yet?) and that on GTK it's set to AUTO
09/18 02:12:59 tlsa
    I thought we were aiming to get all platforms setting that to YES
09/18 02:13:17 hiyuh
    lol
09/18 02:13:20 hiyuh
    http://dev.gentoo.gr.jp/~hiyuh/misc/json-c-configure-in.diff
09/18 02:14:01 hiyuh
    missing double quote :)
09/18 02:15:53 hiyuh
    running ./configure shows mysterious message: "C: command not fond" :D
09/18 02:21:28 jmb
    fun
09/18 02:26:26 hiyuh
    hmm, it still some "C" appears.
09/18 02:43:49 hiyuh
    jmb: libparserutils's DESTDIR fix is incomplete. in "install:"
    all of $(INSTALL) lines have no $(DESTDIR). you just did $(MKDIR)'s?
09/18 02:51:38 hiyuh
    jmb:
    http://dev.gentoo.gr.jp/~hiyuh/misc/libparserutils-more-DESTDIR.patch
09/18 02:55:21 jmb
    whoops. I guess I must've trampled those when I did the fix for
    installing on OS X
09/18 02:56:32 hiyuh
    :)
09/18 03:21:28 hiyuh
    omg
09/18 03:23:00 hiyuh
    jmb: hubbub's make test still fails at html/mangleme.1.html of
    Treebuilding API.
09/18 03:25:31 jmb
    yes
09/18 03:25:34 jmb
    that's a known bug
09/18 03:27:21 hiyuh
    there is no way to skip this test? or it's last one?
09/18 03:28:36 jmb
    no, there isn't
09/18 03:30:08 hiyuh
    ack

つー訳でnet-libs/hubbubの一歩手前で"たいむあっぷ"、続きはまた来週（？）な！！1 :DDD
[Sadly, I couldn't commit net-libs/hubbub. but I'll be back soonish!!1 :DDD]

TLUG.NomiKai++; /* ModSecurity/Detaxe/ss */

二度目のTLUG、今回はModSecurityとDetaxeとscalable storageだった。会場は天下（？）のSun、用賀を見下ろせる27Fのミーティングルーム、エアコンがバリバリで蝶快適。自動販売機にSunのロゴが入っていて、通常の値段よりも30円とか安いのな。荷物搬入のエレベータからしか会場に行けなくて、ちょっと迷ってしまったがな！！1 :P
[It's second time to join TLUG meeting for me. This time is about ModSecurity, Detaxe and OSS scalable storage. T3h location is SUN Microsystems @ YoGa, 27th floor w/ coolest A/C, it's good. T3h automat has Sun logo is, discounts all beverage 30 JPY, it's good. To reach t3h 27th floor, we have to use a lift that looks like mainly for carry big WS in, it's not good. :P]

前回に比べるとプレゼンしてた人が非ネイティブだからか、単にゆっくり喋るのを留意してたのか、何気に聞き取れた気がする。以下、蝶意訳。
「バグってるブツをどうにかする方法はやっぱりバグを直すことだけど、ソースが無かったり、パッチ当てると余計ぶっ壊れたりしてメンドイから防火壁埋め込んで誤魔化そうぜ。だって、ぶっ壊れてるのが分かると俺がボスに怒られるんだもん！！1」
「値段の分からないOEMなソフトウェアなんか要らねーよ、3割も原価喰ってるみたいだし返品しようぜ。オプショナルなら買うかもしれんけどな！！1」
「cman、CLVM、GNBD、GFS2、DRBD、DM-MPにタダ乗りして俺は幸せになる予定だ！！1」
[All of this time's presentation were done by non-native peeps, or they might keep thier mind to speek slowly, it hepls to me to understand what they'd say more than the prev's. So, something like that, "The best way to beat vulnabilities is fixing as bugs though. In case fo w/o source code or proposed patch breaks our system, it's not fun. So just work around by using this FW. B/c everytime this crap goes wrong, boss blames me!!1", "We don't need parasitic OEM software which has unknown price. About 30% of our payment is for these craps, so refund these undesirable tax. OPTIONAL is definitely FTW!!1", "cman, CLVM, GNBD, GFS2, DRBD and DM-MP will make me happy to do OSS free riding!!1"]

一次会はわたみん家@用賀。に行く途中で、何故かSunのjimさんと名刺交換。
matsuuさんが「割り勘負けしない様に喰いまくれ！！1」と言っていたので、テキトーに喰いまくって腹一杯になると、前と同じ様に、ネイティブな方々がペラペラしゃべっている横でヒアリングの真似をするが、相変わらず分からんかった。何かもうね、単語の切れ目とか全然分からんのですけど気のせいですね、そうですね。とか思っていたら、trombikセンセーが来て、「どうよ、俺のプレゼン？」とか仰ったので、自分がネイティブな英語が聞き取れない事を棚に挙げて「話、長ーい」とか「数字を日本語だー」とか茶化した。 :P
[First NomiKai, WataminChi@Yoga, while we were going to, I got jim's name card!!1 :)
matsuu sez "eat, just eat to earn back my 3000 JPY!!1", we're stuffed. Then, we did hearing English who are native speakers sat at our side. O.K. I don't understand what they're talking about, well, they're really speaking English? It's really hard to me to recognize any gap between word-to-word. Then trombik came and asked, "how about mine?". Even if my English skill sucks, but there is no problem to say like "TOO LONG!!1" or "T3H NUMBERS ARE STILL JAPANESE!!1".]

その後、プレゼンの中休みにsmoking roomで「VHDLでメシ喰ってるけど、OpenSPARCはVerilogだから分かんね」とか言ってたのを覚えててくれたSunのshojiさんが来て、まったく関係無いSunの内部情報をリークしてくれた。曰く、「日本語が流暢でない外国人は、自分の思っている事がキチンと相手に伝わらない事にストレスを感じてるのでマネジメントすんの大変なんよ」とか「同僚の外国人と食事に行く事と飯を喰っている時は横文字で話すから、これをヨコメシと言う」とか。おー、何と言う貴重な情報。 :DDD
[After that, I met shoji at smoking room at Sun and mumbled "I prefer VHDL, but OpenSPARC is Verilog", so he came to talk us again, thanks. And he leaks awesome Sun's confidentials like "it's reallly hard to management foreigners in a office live in Japan but who can not speak Japanese very well b/c they're frustrated always, some Japanese doesn't understand completely what they'd saying." or "To lunch w/ foreigners. We, Japanese should speak English (was written on a papar directed left to right, in Japanse, it's YOKO direction) in that time. So it's called YokoMeshi (Meshi means lunch, of cource)." OMG, Sun rock0rz!!1 :DDD]

二次会は店名のフォントが崩れすぎていて読めない"あいりっしゅ"なバー@渋谷。
ちびちびやりながら、いつものtrombikセンセーの日本に対する不満を拝聴する。
以下、その模様を演出を多分に含んだ四行で表現。
「手前ら、学校で英語ならったろ、話せよ」
「ここは日本じゃ、嫌なら外国へでも高跳びしなはれ」
「もうね、この問題と戦わないといけないんよ」
「"この問題と戦わないといけないんよ"という問題と戦わないとな！！1」
とても良い漫才でした、ほんとうにありがとうございました。 :DDD
[Second NomiKai, Irish bar @ ShibuYa, its name can not be read for me b/c strongly-distorted fonts are used. It's time to listen t3h trombik's bitching Japanese like that.
"n00b, you must studied English in your school days, so explain in English!!1", "Here is Japan. There is no problem to speak Japanese. If you don't like Japan, go other countries!!1", "fsck, I'm facing those stupid problem!!1", "Nah, I'm also facing this stupid problem, you!!1"
It's nice ManZai. KTHX. :DDD]

他にも色々話したけど、とりあえず、正しい日本文化を広める為に「DEATH NOTEが好き」と言ってたオランダな人に「銀魂とJOJOがオススメ」とか言っといた。 :P
[To correct Japanese calture, we recommend GinTama and JOJO to a fun of DEATH NOTE, who comes from Netherland. It's for great justice. :P]