JunkCode.karma++; /* br10_stim.c */

問題: このコードは何でしょう？ :9
[Q. This code for what? :9]

#include <stdio.h>
#include <stdint.h>

#define MSK16(i, b)      ((i) & ((uint16_t)0x0001 << (b)))
#define SLL16(i, b)      ((uint16_t)(i) << (b))
#define SLR16(i, b)      ((uint16_t)(i) >> (b))
#define ORG16(i, b)      (SLR16(MSK16((i), (b)), (b)))
#define MOV16(i, b1, b2) (SLL16(ORG16((i), (b1)), (b2)))

uint16_t br10(uint16_t i) {
 uint8_t b;
 uint16_t bri;

 for (bri = 0x0000, b = 0; b < 10; b++) {
  bri |= MOV16(i, b, (10 - 1) - b);
 }

 return bri;
}

int main(int argc, char *argv[]) {
 uint16_t i, bri, brbri;

 for (i = 0x0000; i < SLL16(0x0001, 10); i++) {
  bri   = br10(i);
  brbri = br10(bri);
  printf("%4d <-BR10-> %4d <-BR10-> %4d ... %s\n",
   i, bri, brbri, (i == brbri) ? "OK" : "NG");
 }

 return 0;
}

while(1) Xilinx.ISE->EatMEM(malloc(sizeof(void)));

会社の自分のPCのISEを8.2iか9.2iにversion bumb．bumpではありません．
最近，#-bugsではversion bum*b*が流行りです． :DDD
[Version bumb 8.2i to 9.2i of fsckin' ISE at my local work PC. It's not
typo. You can see t3h rox0rz phrase, version bum*b* at #-bugs
sometimes. :DDD]

メジャーヴァージョンが上がってメモリ効率が良くなったとか，fmax云々だの
騒いでいるけれど，決め手は8.2iのままだと例のFFT IPが今回の用途で
びみょーにbugりそうだから． :p
[T3h 9.2i sez "KK, I WONT EAT UR MEM ANYMORE", "I CAN HAS FMAX
POWERZ". But all reason of what I've bumbed to 9.2i is t3h crappy FFT
IP w/ 8.2i will have a stupid bug for this project use. *STAB* :p]

Answer Record #29427
LogiCORE Fast Fourier Transform (FFT) v4.0
Why do I see incorrect outputs when I simulate an unscaled FFT with
a point size larger than 1024, and the Complex Multiplier Optimize for
Speed option is selected?

昨日のOUTPUTIFの問題は既にモニョモニョして解決した．
現在，awk(1p)な俺様VHDLバックエンドでTSVなファイルからstimulusと
expectationの対をシコシコと生成中．
[T3h Q of OUTPUTIF is already marked as RESO FIXED in this design.
ATM, I've been codin' awk(1p) back end to generate VHDL of the
stimulus and expectation pairs from TSVs.]

週末の予定メモ．
modular texliveをモニョる．
[This weekend plan: Pokin' modular texlive.]
bug #195815

xcg.fft.spec.karma--; /* fsckin' misprints */

XilinxのFast Fourier Transform v4.0のProduct specificationが低品質過ぎる．
タイミングチャートのport名が全然違うとか何考えてんだ？まじありえねー． :P
[Xilinx's Fast Fourier Transform v4.0 Product specification really suX0rz.
*STAB*. Why on the earth did dudes misprint t3h port names on timing chart?
NFC at all, KTHXBYE. :P]

で，なんとかその辺を誤魔化して，件のFFTマクロをでっち上げて，後方互換性の為に
そのまんま入出力のIFを移植した．で，予想通り，動作予定クロックで動かないと言う罠．
以下，出力IFの簡易ヴァージョンとヤル気の無いテストベンチ，さらにその手の人しか
解けないかもしれない問題っぽいモノ．
[For fsckin' backward compat, I've ported previous I/F w/o explicit changes to
t3h FFT macro by using that crap. Yup, ITDOESNTWORK(tm) w/ planning clock
ATM. These are stripped version output IF, dumb test bench, and a practical
VHDL Q.]

問題：どこがクロック高速化のボトルネックか？出来れば修正を施して示せ．
なお，OUTPUTIF.vhdlへの修正はoDATA，oOVRそれぞれのレイテンシー
は適当に増やして構わないが，修正以前と同様にアラインメントが揃っている
と好ましい．
[Q: Whre is fsckin' bottleneck to increase clock speed? Fix0rz it. You can
increase latencies of oDATA and oOVR as you like, and to sort their
alignment would be good for following ones.]

修正：typoとか．
[FIX: for typos.]

--
-- OUTPUTIF.vhdl
--
library ieee;
use ieee.std_logic_1164.all;

entity OUTPUTIF is
    port (
        iCLK  : in  std_logic;
        iCLR  : in  std_logic;
        iDATA : in  std_logic_vector(22 downto 0);
        iGAIN : in  std_logic_vector( 3 downto 0);
        oDATA : out std_logic_vector(11 downto 0);
        oOVR  : out std_logic
    );
begin
end entity OUTPUTIF;

architecture RTL of OUTPUTIF is

begin

    -- Tune Gain and OVeRflow detection
    P_TG_OVR : process (iCLK)
    begin
        if (iCLK'event and iCLK = '1') then
            if (iCLR = '1') then
                oDATA <= (others => '0');
                oOVR  <= '0';
            else
                case iGAIN is
                    when "0000" => -- 2^0
                        oDATA <= iDATA(22 downto 11);
                        oOVR  <= '0';
                    when "0001" => -- 2^1
                        if (iDATA(22 downto 21) = "00" or
                            iDATA(22 downto 21) = "11") then
                            oDATA <= iDATA(21 downto 10);
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "0010" => -- 2^2
                        if (iDATA(22 downto 20) = "000" or
                            iDATA(22 downto 20) = "111") then
                            oDATA <= iDATA(20 downto 9);
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "0011" => -- 2^3
                        if (iDATA(22 downto 19) = "0000" or
                            iDATA(22 downto 19) = "1111") then
                            oDATA <= iDATA(19 downto 8);
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "0100" => -- 2^4
                        if (iDATA(22 downto 18) = "00000" or
                            iDATA(22 downto 18) = "11111") then
                            oDATA <= iDATA(18 downto 7);
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "0101" => -- 2^5
                        if (iDATA(22 downto 17) = "000000" or
                            iDATA(22 downto 17) = "111111") then
                            oDATA <= iDATA(17 downto 6);
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "0110" => -- 2^6
                        if (iDATA(22 downto 16) = "0000000" or
                            iDATA(22 downto 16) = "1111111") then
                            oDATA <= iDATA(16 downto 5);
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "0111" => -- 2^7
                        if (iDATA(22 downto 15) = "00000000" or
                            iDATA(22 downto 15) = "11111111") then
                            oDATA <= iDATA(15 downto 4);
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "1000" => -- 2^8
                        if (iDATA(22 downto 14) = "000000000" or
                            iDATA(22 downto 14) = "111111111") then
                            oDATA <= iDATA(14 downto 3);
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "1001" => -- 2^9
                        if (iDATA(22 downto 13) = "0000000000" or
                            iDATA(22 downto 13) = "1111111111") then
                            oDATA <= iDATA(13 downto 2);
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "1010" => -- 2^10
                        if (iDATA(22 downto 12) = "00000000000" or
                            iDATA(22 downto 12) = "11111111111") then
                            oDATA <= iDATA(12 downto 1);
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "1011" => -- 2^11
                        if (iDATA(22 downto 11) = "000000000000" or
                            iDATA(22 downto 11) = "111111111111") then
                            oDATA <= iDATA(11 downto 0);
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "1100" => -- 2^12
                        if (iDATA(22 downto 10) = "0000000000000" or
                            iDATA(22 downto 10) = "1111111111111") then
                            oDATA <= iDATA(10 downto 0) & '0';
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "1101" => -- 2^13
                        if (iDATA(22 downto 9) = "00000000000000" or
                            iDATA(22 downto 9) = "11111111111111") then
                            oDATA <= iDATA(9 downto 0) & "00";
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "1110" => -- 2^14
                        if (iDATA(22 downto 8) = "000000000000000" or
                            iDATA(22 downto 8) = "111111111111111") then
                            oDATA <= iDATA(8 downto 0) & "000";
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when "1111" => -- 2^15
                        if (iDATA(22 downto 7) = "0000000000000000" or
                            iDATA(22 downto 7) = "1111111111111111") then
                            oDATA <= iDATA(7 downto 0) & "0000";
                            oOVR  <= '0';
                        else
                            oDATA(11) <= iDATA(22);
                            oDATA(10 downto 0) <= (others => not iDATA(22));
                            oOVR  <= '1';
                        end if;
                    when others => -- 2^0
                        oDATA <= iDATA(22 downto 11);
                        oOVR  <= '0';
                end case;
            end if;
        end if;
    end process P_TG_OVR;

end architecture RTL;

--
-- BENCH_OUTPUTIF.vhdl
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity BENCH_OUTPUTIF is
begin
end entity BENCH_OUTPUTIF;

architecture BENCH of BENCH_OUTPUTIF is

    component OUTPUTIF is
        port (
            iCLK  : in  std_logic;
            iCLR  : in  std_logic;
            iDATA : in  std_logic_vector(22 downto 0);
            iGAIN : in  std_logic_vector( 3 downto 0);
            oDATA : out std_logic_vector(11 downto 0);
            oOVR  : out std_logic
        );
    end component OUTPUTIF;

    signal sCLK  : std_logic;
    signal sCLR  : std_logic;
    signal sDATA : std_logic_vector(22 downto 0);
    signal sGAIN : std_logic_vector( 3 downto 0);

    signal sOUTPUTIF_oDATA : std_logic_vector(11 downto 0);
    signal sOUTPUTIF_oOVR  : std_logic;

begin

    P_CLK : process
    begin
        sCLK <= '1'; wait for 0.5 us;
        sCLK <= '0'; wait for 0.5 us;
    end process P_CLK;

    P_CLR : process
    begin
        sCLR <= '1'; wait for 10.0 us;
        sCLR <= '0'; wait;
    end process P_CLR;

    P_DATA : process (sCLK)
    begin
        if (sCLK'event and sCLK = '1') then
            if (sCLR = '1') then
                sDATA <= (others => '0'); -- signed zero
            else
                sDATA <= signed(sDATA) + 1;
            end if;
        end if;
    end process P_DATA;

    P_GAIN : process (sCLK)
    begin
        if (sCLK'event and sCLK = '1') then
            if (sCLR = '1') then
                sGAIN <= (others => '0'); -- unsigned zero
            else
                if (signed(sDATA) = 0) then
                    sGAIN <= unsigned(sGAIN) + 1;
                else
                    sGAIN <= sGAIN;
                end if;
            end if;
        end if;
    end process P_GAIN;

    U_OUTPUTIF : OUTPUTIF
    port map (
        iCLK  => sCLK,
        iCLR  => sCLR,
        iDATA => sDATA,
        iGAIN => sGAIN,
        oDATA => sOUTPUTIF_oDATA,
        oOVR  => sOUTPUTIF_oOVR
    );

end architecture BENCH;

Suspend(&ADJJV); read(xcg.fft.spec, &me, ALL);

ADJJVが一段落，まだおわってないけど．記念にあとでSLOCのグラフも作っとくかな．
[I'd suspend to be codin' ADJJV, (is not completed yet). I'll make its
SLOC trend graph as a ceremonial crap soonish.]

続いて，XilinxのCoreGenのFFTの英語な仕様書を読む予定．
なんでも，あるブツがLX200なボードに入りきらんので，FFTの部分をソイツに取り替えた上で，
動作速度を上げる事で回路容量を減らすんだとか．
ボス曰く，ストリーム処理の回路容量を減らす為に，多入力多出力同一回路を単一回路にして，
動作速度をその分上げて，入力後段MUX+FIFOと出力前段にDEMUX+FIFOな感じすればいい，と．
今でも128MHzで動いてるのにホントに大丈夫なんかな？ :9
[Then, I'd have to read fsckin' Xilinx CoreGen's FFT spec written in English.
To diet bloated t3h macro, my bosses sez "multiple input/output macro
has some identical inside sub-macro, FFT that is. The plain is to rip it
for making it be unified. Plus, input MUX+FIFO and output DEMUX+FIFO,
then input faster clock, period."
...Oh dear, I'd have to say "yes sir", but WTF? :)]

bus(eBIDIRECT).collison.karma--;

#vhdl@irc.freenode.netで双方向バスの話．
[Here is snippet log of #vhdl@irc.freenode.net.
The subject is bidirectional bus.]

10/13 23:48:13 joe2371
    I do not understand iobuf.  What happens if I is driven to (NOT IO)?
    Which input wins?
10/13 23:50:28 joe2371
    Would this condition tie Vcc to ground?
10/13 23:57:15 joe2371
    Do I use T to select input vs. output mode?  The table I have in my
    documentation does not make this clear to me.
10/14 00:08:35 joe2371
    I am going to assume that the table is simply unclear and the
    schematic symbol probably represents a combination of obuft with
    ibuf.  That would make a lot of sense, but I am surprised that the
    Xilinx documentation would describe the operation the way it does.
    Unless my original interpretation of the documentation is correct and
    I need to use seperate ibuf and obuft components in my design.  Ugh.
10/14 00:23:54 joe2371
    Please look at this and tell me if I am right or wrong. Thank
    you. http://rafb.net/p/y1DT3Y68.html
10/14 00:30:40 joe2371
    Hans, can you please answer my question if you have time?
    http://rafb.net/p/y1DT3Y68.html
(BEGIN_SNIPPET_FROM_THE_LINK)
iobuf
 
 T ____
       |
     |\|
 I __| \______ IO
     | /   |
     |/    |
       /|  |
 O ___/ |__|
      \ |
       \|
 
 
Xilinx iobuf table:
 
T I IO O
1 X Z X
0 1 1 1
0 0 0 0
 
But I think I want this:
 
T I IO O
1 X 0 0
1 X 1 1
0 0 0 X
0 1 1 X
 
Is this what I get?
(END_SNIPPET_FROM_THE_LINK)
10/14 00:31:57 joe2371
    I am trying to learn how to use the iobuf component and the
    documentation is not clear to me.
10/14 00:33:12 joe2371
    And I don't know how to test my understanding in simulation because
    it is a buffer.
10/14 01:31:34 hiyuh
    joe2371: did you understand...
10/14 01:31:46 hiyuh
    1. "I is input from inside of FPGA, to output to IO"?
10/14 01:31:53 hiyuh
    2. "O is output from outside of FPGA, to input from IO"?
10/14 01:31:55 hiyuh
    3. "buffered I and unbuffered O is shared at inside of FPGA"?
10/14 01:32:33 joe2371
    IO is pin side. I,O are FPGA side, right?
10/14 01:32:47 hiyuh
    yup
10/14 01:33:23 joe2371
    does T select input/output mode?  I mean, what happens if I is 0
    but IO goes to 1?
10/14 01:35:19 joe2371
    I mean, if SRAM is driving IO, how do I disable I from trying to
    drive it also?
10/14 01:36:08 joe2371
    Do I have to output Z to the I?
10/14 01:37:07 hiyuh
    nope, T selects buffered I's state (it may not be IO's state) to 'Z'
    (T = 1) or unbuffered I (T = 0).
10/14 01:38:13 joe2371
    So T disables the I pin of the iobuf, but does prevent IO from
    changing O?
10/14 01:40:12 joe2371
    I am trying to learn how to read the value of IO into the FPGA.
10/14 01:42:06 joe2371
    I guess I still don't understand. And I have not been able to simulate
    an iobuf to learn how it works. :-/
10/14 01:44:20 joe2371
    Maybe you have answered my question already.  If T=1 makes I=Z,
    then hopefully O=IO.
10/14 01:45:46 joe2371
    I am sorry if I do not immediately understand your explanation.
10/14 01:52:39 hiyuh
    "if T <= 1, then buffered I <= 'Z' and O <= IO", "if T =
    0, buffered I <= I. so O and IO <= wired(buffered I, IO comes
    from as others' output)"
10/14 01:53:44 joe2371
    Thank you.  I think that is exactly what I want.
10/14 01:53:55 hiyuh
    yw
10/14 01:57:27 hiyuh
    ... so bus collision make your day, I guess. :p
10/14 01:57:35 hiyuh
    s/make/makes/
10/14 01:57:36 *
    hiyuh runs.
10/14 01:59:37 hiyuh
    FYI, to read about "I-BEFORE" and "OUT-AFTER" for ucf files' timing
    constrain would be useful.
10/14 01:59:53 hiyuh
    s/I-/IN-/
10/14 02:00:31 joe2371
    oh, no.  This means "O and IO <= wired(I, IO comes from SRAM)"
    means two inputs on same bus.  That is not what I want, of course.
10/14 02:01:34 hiyuh
    yeah
10/14 02:02:13 joe2371
    "assign IO = I and assign IO = SRAM-output" at the same time is not
    what I want.  Does this mean I cannot use iobuf for my design?
10/14 02:03:05 joe2371
    I will look for "I-BEFORE" and "OUT-AFTER" for ucf files.
10/14 02:07:54 hiyuh
    so, to keep IO <= 'Z' w/ T = '1' as neutral. when you really want
    to output via IOBUF, make sure SRAM is input-state before output
    via IOBUF. when others, you should think SRAM may be output-state.
10/14 02:08:53 joe2371
    oh, I see.
10/14 02:08:56 hiyuh
    otherwise, bus collisoin makes your day. :p

snipLog("/me@#vhdl");

久しぶりにIRCのログを貼り付けてみる．
#vhdl@irc.freenode.netでMemory I/Fなお話．
[Here is a snippet log #vhdl@irc.freenode.net. The subject is a memory I/F.]

10/13 04:14:34 joe2371
    Are questions about schematics portable between languages and
    software?  I'm trying to find out the correct way to connect one
    signal to two FPGA pins.  Do I want to treat my signal as a 1-bit bus
    and put two taps on it?  I thought that bus taps required the nets
    on both sides to have compatible names (eg: Addr(19:0) -> Addr(15)
    and not Addr(19:0) -> Foo).  Is this splitting best done in the pin
    assignment file (.ucf) ?
10/13 04:28:44 hiyuh
    depends on transfer speed, imho.
10/13 04:32:33 hiyuh
    e.g. I'm now working 8 boards (each one has 4 virtex4).
10/13 04:33:21 hiyuh
    each virtex4 will input/output from/to others, the data syncs 128MHz
    via simple parallel bus.
10/13 04:33:26 hiyuh
    the output to outside of the board will be syncs 256MHz as LVDS.
10/13 04:33:38 hiyuh
    sample pic is http://dev.gentoo.gr.jp/~hiyuh/misc/V4LXB.jpg
10/13 04:35:12 hiyuh
    reference clock's accuracy and deskewing of sync clock is also PITA.
10/13 04:35:32 hiyuh
    s/is/are/
10/13 04:38:47 joe2371
    That's a nice looking board.  The Virtices have fans on them?
10/13 04:39:58 hiyuh
    yup
10/13 04:41:38 hiyuh
    the left side one is japanese tobacco box, btw.
10/13 04:41:59 joe2371
    With the letter C ?
10/13 04:42:10 hiyuh
    yeah
10/13 04:43:12 joe2371
    pretty neat.  I'd hate to think what it costs.
10/13 04:44:27 joe2371
    Do tools exists that can map a design across multiple chips
    automatically?
10/13 04:45:51 joe2371
    ...basically treating four FPGAs like one larger one, I mean.
    The more I think about it, the less likely I imagine that is.
10/13 04:46:02 hiyuh
    my bosses said, one Virtex4 LX200 (the best one of Virtex4 LX series)
    will costs about 1000000 yen. but it should depends on quantities
    of order, I guess. :p
10/13 04:47:05 joe2371
    It's something like 1000 yen to the dollar, I think.  Ouch.
10/13 04:47:43 hiyuh
    I dunno that neat tool which automatically map it to them.
10/13 04:48:29 joe2371
    I guess if they are Virtex chips, you are stuck with Xilinx tools.
10/13 04:49:39 hiyuh
    yeah, it's kinda corporate (or project's?) policy, maybe.
10/13 04:50:48 hiyuh
    so I can take a screenshot of fsckin' ISE crashing per working day. :p
10/13 04:51:15 joe2371
    Only once per day?  ISE crashes sometimes 3-5 times on me.
10/13 04:51:50 joe2371
    At least it recovers my work OK. (so far)
10/13 04:52:49 hiyuh
    I'd have to treat that crap *gently*, b/c it's my job atm. :p
10/13 04:55:31 hiyuh
    well, using same name in sch and logical vhdl design is a bit of
    difficult, if it's a dead-lined project.
10/13 04:57:03 hiyuh
    and ucf craps are not only for constraining the pin assign.
10/13 04:57:40 hiyuh
    splitting them to ucf is a good way to go, though.
10/13 04:57:44 joe2371
    Ok. My lab homework assignment is to create a 1MB memory controller
    with only 14 address pins.  I am trying to connect one signal to
    two memory chips (same signal, different pins).
10/13 04:58:04 hiyuh
    heh
10/13 04:58:09 joe2371
    I created that 1-bit bus with two taps.
10/13 04:58:16 joe2371
    I don't know if it works, though.
10/13 05:00:58 hiyuh
    have you consider about the memories' I/F, driving load, or something?
10/13 05:01:19 hiyuh
    s/consider/considered/
10/13 05:02:16 joe2371
    oh, no.  I am still experimenting with my initial concept for
    the design.  I don't know what difficulties to expect.
10/13 05:03:31 hiyuh
    ah, ok. then first step is to gaze the memories' spec sheet, I
    guess. :)
10/13 05:03:49 joe2371
    The documentation for the board did not talk about driving load
    that I can remember.  It just says which pins of the FPGA are tied
    to which pins of the SRAMs
10/13 05:04:04 joe2371
    I have the specs for the SRAM here
10/13 05:05:17 hiyuh
    SRAM? then it doesn't need to be refreshing, right?
10/13 05:05:25 joe2371
    right
10/13 05:05:39 joe2371
    yes, I am lucky it is SRAM
10/13 05:06:18 joe2371
    But I am unlucky I have only 14 address bus pins connected.
10/13 05:07:50 hiyuh
    SRAM's address is 14bits?
10/13 05:08:02 hiyuh
    or you have only 14bits on FPGA to specify SRAM's address but SRAM's
    address is not 14bits?
10/13 05:09:38 joe2371
    no, 18 bits for a 16-bit memory location, plus upper byte and lower
    byte pins, plus there are two chips.  So SRAMs actually have 20-bit
    address (of bytes).  But I have a CPU which has only 14 address pins
    connected to the FPGA.
10/13 05:10:12 joe2371
    I want to use the LSB of the address to select upper/lower byte.
    And LSB+1 to select SRAM0/SRAM1.
10/13 05:10:34 joe2371
    the missing MSBits are provided from a register tied to a port.
10/13 05:11:16 joe2371
    but I need to connect the LSB and LSB+1 to four pins.
10/13 05:11:28 hiyuh
    oic
10/13 05:14:44 joe2371
    I just thought of something.  If chip enable is off, these SRAMs
    go to low power mode.  Maybe I should organize my pins differently
    so that I will use less power when the memory is less than half
    full... Hmmm... I'll think about that.
10/13 05:16:22 joe2371
    I think it means changing one line of HDL.  Then I can say my design
    not only works, but is also efficient. :-)
10/13 05:17:43 joe2371
    Nevermind.  CE only goes high on reads and writes.  It does not
    matter if the memory contains data.  (/me needs more coffee)
10/13 05:17:56 hiyuh
    yeah, "separated CEs and shared others" sound good to me though.
10/13 05:18:38 joe2371
    the data pins are not shared, though.  Address pins are.  But UB/LB/CE
    are not shared either.
10/13 05:21:26 joe2371
    the SRAM data sheet talks about "test load" only.
10/13 05:21:49 hiyuh
    I guess "when CE is disabled, it doesn't care other signals". why
    not shared address/data bus for that?
10/13 05:22:19 joe2371
    They want you to be able to read 32 bits at one time, I think.
10/13 05:22:31 hiyuh
    ah ok
10/13 05:23:25 joe2371
    they do have shared address, though.
10/13 05:23:40 hiyuh
    heh
10/13 05:25:25 joe2371
    Since the connection between SRAM and FPGA cannot be changed, then I
    think I can't think of anything I can do about the load from inside
    the FPGA.
10/13 05:26:08 joe2371
    s/I\ think\ I\ can't\ think\ of/I can't think of/
10/13 05:26:23 hiyuh
    well, the spec sheet should have typ val of rw timing by pic or
    table. so all what you do may be to constrain some timing of FPGA's
    output.
10/13 05:27:05 joe2371
    The SRAM is about 200 times faster than my CPU and is almost as fast
    as the FPGA.
10/13 05:29:02 joe2371
    My guess is that the SRAM will provide data long before the CPU
    tries to read it.  I hope I don't have too many timing problems.
10/13 05:31:57 hiyuh
    deskewing for I/O like feedback path may have many timing problems,
    too bad. ;p
10/13 05:33:10 hiyuh
    only for output has little problem of timing (like for D/A), iirc.
10/13 05:33:40 joe2371
    Do you know somewhere I can read more about this?
10/13 05:33:47 joe2371
    What should I search for?
10/13 05:35:02 hiyuh
    deskewing is common issue for FPGA design, see I/O and clock
    management section of your device's users guide.
10/13 05:35:12 joe2371
    oh, ok
10/13 05:35:20 hiyuh
    good luck :)
10/13 05:35:34 joe2371
    thanks. :-/
10/13 05:37:49 joe2371
    "skew" was not found in the documentation. :-/
10/13 05:39:32 hiyuh
    lol, what's your device?
10/13 05:40:08 joe2371
    Digilent starter board with spartan3
10/13 05:42:35 joe2371
    I found this in a referenced document "Digital Clock Managers also
    eliminate clock skew"
10/13 05:43:19 hiyuh
    yeah, DCM is a way for deskewing. :)
10/13 05:44:06 joe2371
    I have 4 of them, it looks like.
10/13 05:47:19 hiyuh
    well, maybe you want to use DCM_BASE or DCM_PS, I guess.
10/13 05:47:36 joe2371
    I'll look them up. Thanks.
10/13 05:47:51 hiyuh
    yw

Xilinx.ISE.karma--; /* MSVC++ runtime error!!1 */

今日のクラッシュ，もう何も言うまいて． :p
[Today's crash. All what I can say is only "WTF". :p]

JunkCode.karma++; /* csa_stim.c */

問題: このコードは何でしょう？ :9
[Q. This code for what? :9]

#include <stdio.h>
#include <stdint.h>
#include <string.h>

uint8_t do_csa(uint8_t *pa, uint8_t *pb)
{
 uint8_t a_xor_b, a_and_b;

 a_xor_b = *pa ^ *pb;
 a_and_b = *pa & *pb;

 *pa = a_xor_b;
 *pb = a_and_b << 1;

 return (a_and_b >> 7);
}

char *uint8_to_str(char *pstr, uint8_t q)
{
 switch (q & (uint8_t)0xF0) {
  case (uint8_t)0x00 : strcpy(&pstr[0], "0000"); break;
  case (uint8_t)0x10 : strcpy(&pstr[0], "0001"); break;
  case (uint8_t)0x20 : strcpy(&pstr[0], "0010"); break;
  case (uint8_t)0x30 : strcpy(&pstr[0], "0011"); break;
  case (uint8_t)0x40 : strcpy(&pstr[0], "0100"); break;
  case (uint8_t)0x50 : strcpy(&pstr[0], "0101"); break;
  case (uint8_t)0x60 : strcpy(&pstr[0], "0110"); break;
  case (uint8_t)0x70 : strcpy(&pstr[0], "0111"); break;
  case (uint8_t)0x80 : strcpy(&pstr[0], "1000"); break;
  case (uint8_t)0x90 : strcpy(&pstr[0], "1001"); break;
  case (uint8_t)0xA0 : strcpy(&pstr[0], "1010"); break;
  case (uint8_t)0xB0 : strcpy(&pstr[0], "1011"); break;
  case (uint8_t)0xC0 : strcpy(&pstr[0], "1100"); break;
  case (uint8_t)0xD0 : strcpy(&pstr[0], "1101"); break;
  case (uint8_t)0xE0 : strcpy(&pstr[0], "1110"); break;
  case (uint8_t)0xF0 : strcpy(&pstr[0], "1111"); break;
  default            : strcpy(&pstr[0], "????"); break;
 }

 switch (q & (uint8_t)0x0F) {
  case (uint8_t)0x00 : strcpy(&pstr[4], "0000"); break;
  case (uint8_t)0x01 : strcpy(&pstr[4], "0001"); break;
  case (uint8_t)0x02 : strcpy(&pstr[4], "0010"); break;
  case (uint8_t)0x03 : strcpy(&pstr[4], "0011"); break;
  case (uint8_t)0x04 : strcpy(&pstr[4], "0100"); break;
  case (uint8_t)0x05 : strcpy(&pstr[4], "0101"); break;
  case (uint8_t)0x06 : strcpy(&pstr[4], "0110"); break;
  case (uint8_t)0x07 : strcpy(&pstr[4], "0111"); break;
  case (uint8_t)0x08 : strcpy(&pstr[4], "1000"); break;
  case (uint8_t)0x09 : strcpy(&pstr[4], "1001"); break;
  case (uint8_t)0x0A : strcpy(&pstr[4], "1010"); break;
  case (uint8_t)0x0B : strcpy(&pstr[4], "1011"); break;
  case (uint8_t)0x0C : strcpy(&pstr[4], "1100"); break;
  case (uint8_t)0x0D : strcpy(&pstr[4], "1101"); break;
  case (uint8_t)0x0E : strcpy(&pstr[4], "1110"); break;
  case (uint8_t)0x0F : strcpy(&pstr[4], "1111"); break;
  default            : strcpy(&pstr[4], "????"); break;
 }

 return pstr;
}

int main(int argc, char *arcv[])
{
 uint8_t a, b;
 uint8_t a_add_b;
 uint8_t a_csa, b_csa;
 uint8_t n_csa;
 char a_str[] = "00000000";
 char b_str[] = "00000000";

 for (a = 0; a < (uint8_t)0x80; a++) {
  for (b = 0; b < (uint8_t)0x80; b++) {
   a_add_b= a + b;

   a_csa = a;
   b_csa = b;
   n_csa = 0;
   do {
    printf(" CSA(%s, %s)",
     uint8_to_str(a_str, a_csa),
     uint8_to_str(b_str, b_csa));
    do_csa(&a_csa, &b_csa);
    n_csa++;
    printf(" = (%s, %s) ... %d\n",
     uint8_to_str(a_str, a_csa),
     uint8_to_str(b_str, b_csa), n_csa);
   } while (b_csa != (uint8_t)0x00);

   printf("%02X | %02X || %02X | %02X || %s\n",
    a, b, a_add_b,
    a_csa, (a_add_b != a_csa) ? "NG" : "OK");
  }
 }

 return 0;
}

Xilinx.ISE.karma--; /* Stack corrupted!!1 */

ISEが低品質過ぎます，仕事じゃなかったらこんなブツは速攻でabandonだな． :(
[ISE really suXX0rz!!1 All why the hell I can not abandon this crap is b/c it's my job ATM.]

何してたかと言うと，200bitsのバスを隣のFPGAに突っ込むので，ボード上でのタイミング制約
を課す為に物理パッドの論理集合を作っていた．
どうみても固定長配列での集合演算ルーチンです，本当にありがとうございました． :P
[So what I did is to create logical group from physical pads to constrain
bus I/O timing between 2 FPGAs.
That *is* fsckin' set operation routines w/ fixed length array, thank god. :p]

修正：
slangだらけの英語追加．
[Add fskin' my Eng'r'ish.]

GentooJP.NomiKai++; /* OSC 2007 Fall */

京急蒲田の辺りでOSC 2007 Fallでした．
[OSC 2007 Fall @ Keikyu-Kamata.]

今回は開始早々から遥々福井県からmasayukoさん達が参加してくれました．
masayukoさんはGentooJP Java leadな方です，多分． :p
[Dudes came from Fukui-pref. masayuko, AKA GentooJP Java lead... J/K. :p]

展示の方はamd64, x86, ppcのノートPC三台で，全てがタイル型ウィンドウマネージャ
(awesome x2, wmii x1)と言う基本構成で，matsuuさんはデモ用にLive CD 2007.0
も動作させていました．両隣のNetBSDの中の人達やsuseの中の人達とムニャヘニャしつつ，
「にーはお」と言う変な中華料理屋でのお昼を挟んで展示を見に来て頂いた人達にebuildの中身
を説明したり，SH*な人にアドバイスしたりとか．
[Exhibiting w/ 3 laptops. amd64, x86 and ppc, all laptop is running w/ tiling
window manager (awesome x2, wmii x1)． Of course, we did w/ Live CD 2007.0
to demo. Talking w/ NetBSD and suse dudes sometimes. Lunch at "Ni-Hao".
And I've explained ebuild inside or minor arch maintenance policy for FreeBSD
and SH* guys.]

夕方からは飲み会．とりあえず，idaniさんの案内で蒲田の手羽先なお店に入った．
trombik先生のOpenBSD節を基本に，レイヤの高いお話などなどが展開されておりましたので，
レイヤの低い私には理解出来ない所が多々ありましたが，そんな事は気にしません． :D
[OSC was over, then we went to do NomiKai, first one is Tebasaki by idani.
Trombik talk passionately about OpenBSD, and something about higher layers'
that's what I can not understand a bit, but it's not problem. :D]

で，trombik先生オススメ(?)の冥土喫茶に突撃したが，満席と言う罠．
「いってらっしゃいませ，ごしゅじんさま」ってマジで言うのか． :DDD
[Then, trombik leads to his favorite Maid-Cafe.
But all the tables have been taken.
"itte rassyai mase, goshujin-sama" really rock0rz. :DDD]

更に，お好み焼き屋で二次会．
北海道vs福井県とか，日本はもうダメだとか，でも日本のお笑いには将来性があるとか，
スカパーのディスカバリーチャンネルを見ていると仕事にならねーとか．
[Second one is Okonomi-Yaki.
Hokkai-Do vs Fukui-Pref, Japan has no IAP but Japanese comedy has IAP,
Discovery channel of sky prefect TV made us sometimes "WTF".]

masayukoさんは日曜日にお子さんの運動会があるので，10時位に切り上げ．
上野まで御一緒させてもらいました．それから夜行列車で福井まで戻るそうで，大変だ！
乗り換えギリギリまでjavaの話とかをしていたので慌しくなってしまいましたが，
また話が出来ればいいですね． ;)
["Time to call it a night", at about 10:00 PM.
I came back w/ masayuko till the train arrived at Ueno.
We've been talking about java or something, so masayuko almost
missed its stop, though. Let's get together soon. :)]

LX200 = pow(10, 6) * YEN; pOSC->bugz(eLIVE);

今，遊んでいるVirtex4なブツ．
[This is Virtex4 board I'm codin' for.]

Virtex4はLX, SX, FXの三種類，それぞれロジック，DSPとメモリ，I/Oに特化している（らしい）．
LX200はLXシリーズの最高クラスのブツ．で，こいつLX200が四つ載っている．
LX200は百万円/個だとボスが言っていた．つまり，ボード一枚の部品代で四百万円．
そんなんが八枚もこの青い箱の中に入っている． :DDD
[Virtex4 has 3 series LX, SX and FX. They are for logic performance,
DSP and memory, I/O oriented. LX200 is highest one of LX series.
This board has 4 LX200s. LX200 costs about 1000000 yen, my bosses said.
Well, so 8 boards are in this blue box, so WTF? :DDD]

で，その蝶高級ボードに突っ込む予定のヘタレVHDLはこんな感じでSLOCが膨れ上がっています． :)
[An VHDL test sources for t3h boards are being now bloated by me. :)]


ところで明日はOSCです．bugdayな感じでテキトーにやりますのでヒマな方はお越し下さい． :)
[BTW, 10/6 is OSC, it will be bugday. Let us fix0rz bugz? :)]

I HAS 1337 VHDL. LOL!!1

この野郎，思わず爆笑しそうになったじゃねーか！！１ :DDD
[WTF, I'D LOLZ!!1 :DDD]