131MHz, TDS, BK in VHDL #2

そろそろ例のマクロのコーディングに区切りが着くっぽい．
ムニャヘニャした結果，131MHzくらいで動きそうな感じ． :)
そんな今日のdiffstatはー．
[So, that macdo coding will finish.
I've poked it and tested, then it may work with 131MHz clock as maximum. :)
Here's today's diffstat!]

 b/compile/DPNC_TOP.vhd |  204 +++++++++++++++++++++++++
 vhdl/DPNC.vhd          |   14 +
 vhdl/IXSW_MOD.vhd      |    6 
 vhdl/RCTRL_MOD.vhd     |  391 +++++++++++++++++++++++++++----------------------
 vhdl/WCTRL_MOD.vhd     |  231 ++++++++++++++++------------
 5 files changed, 574 insertions(+), 272 deletions(-)

ちょっと物足りないのは内部レイテンシを仕様に合わせる為に，
代入タイミングを変えたり，
非同期なゲート処理をprocess文に埋め込んだりしたから．
[Well, yeah, it got under 1kSLOC.
That's why, today's work is not code stuff,
I've fixed by changing some signal substitute schem and/or
make async-flavor logics embed into process statements for internal latencies issue.]

更に今日悟った事は，
次のP_CASEとP_IFプロセスは全然違うブツだと言う事．
[Then, I realized these process, P_CASE and P_IF are completely different scheme.]

P_CASE : process (ixRST, iCLK)
begin
    if (ixRST = '0') then
        oDECODE <= (others => '0');
    elsif (iCLK'event and iCLK = '1') then
        case iMODE is
            when cMODE1 =>
                oDECODE <= cCODE1;
            when cMODE2 =>
                oDECODE <= cCODE2;
            :
            :
            when others =>
                oDECODE <= cCODE_INVALID;
        end case;
    end if;
end process;
:
:
P_IF : process (ixRST, iCLK)
begin
    if (ixRST = '0') then
        oDECODE <= (others => '0');
    elsif (iCLK'event and iCLK = '1') then
        if (iMODE = cMODE1) then
            oDECODE <= cCODE1;
        elsif (iMODE = cMODE2) then
            oDECODE <= cCODE2;
        :
        :
        else
            oDCODE <= cCODE_INVALID;
        end if;
    end if;
end process;