SIGERRFREE

祝エラーフリー，BER < 10^-7 @ 16QAM 3/4． :DDD
[LOL, SIGERRFREE now. BER < 10^-7 @ 16QAM 3/4. :DDD]

が，受信側PHY下位層のCCAに自分の送信信号が引っかかる問題が発覚．
そう言えば，送信側PHY下位層のステートマシンとこの部分のステートマシン，
別々だった．エレガントに修正しようとした所，ボスに割り込みをかけられ，
モチベーション低下． :(((
[Oh wait. CCA of under-layer than RX PHY sometimes mis-detects
own TX signal as others'. Hmm, FSM in the macros of under-layer than
TX PHY is isolated from under-layer than RX PHY's, ZOMG. I'd have to
fix it ASAP though my boss interrupts my fix0rz, dunno why...]

なので月末恒例の社内飲み会でコーラをがぶ飲みして，修正は明日にして
帰って来た．ゴールデンウィーク？知らんな，そんなもん． :P
[Blah, it drains my motivation completely. So I scored Coke at where t3h
monthly NomiKai b/c mark this bug LATER. I'll fix it tomorrow.
Eh, golden week? I dunno that craps. :P]

修正：b/c typos :P
[FIX: b/c typos :P]

DiffStat(pRepo, rc31, rc32);

今日の分．
入出力レイテンシを考慮して，無効な出力を禁止する処理を追加．
内部及び出力オーバフロー処理を追加して，一部ユニティゲインを調整．
firmwareにする為にISEでムニョらせて只今絶賛放置プレイ中． :P
[Here's today's one.
Reconsider input to output latencies, then make it inhibit invalid output.
Fix for internal and external overflow ceiling/flooring w/ tuning t3h
unity gain. To convert it to firmware needs to do it w/ retarded ISE craps. :P]

 bench/DUMB_RF.vhd  |   17 ++-
 vhdl/AGC_CA.vhd    |    6 -
 vhdl/AGC_FA.vhd    |  269 ++++++++++++++++++++++++++---------------------------
 vhdl/DMFx8.vhd     |    9 +
 vhdl/IPFx8.vhd     |    2 
 vhdl/PWRC.vhd      |   32 +++---
 vhdl/QDM_BPF.vhd   |   10 +
 vhdl/UGT.vhd       |   27 ++++-
 vhdl/UND_BLOCK.vhd |  124 ++++++++++++------------
 vhdl/UNI_BLOCK.vhd |   90 ++++++++---------
 vhdl/UNP_BLOCK.vhd |   54 ++++++----
 11 files changed, 337 insertions(+), 303 deletions(-)

AGCをモニョる事が出来る人間が居ないらしいので，
何故か次のブツのAGCも担当する事になっているっぽい．
ゲイン調整をする事自体が目的ではないので行列計算が出来る位，
ハードウェア側にリソースは与えられないし，PIDはそろそろ飽きた．
昔，スライディングモード制御をヘニョった記憶があるので，
有理数型のスライディングモード制御マクロとかで． :P
[TTT, b/c there is no one who can treat AGC ATM, I'd have to do it
for next project as well. IRL, tunig RF/IF bound gain is not main
propose of the project. Yup, matrix OPs capable resource is not available
and tuning PID paramter is bit of dull. IIRC, I've poked sliding mode
control method. So rational arithmetic sliding mode control macro
is a way to go? :P]

DiffStat(pRepo, beta16, rc31);

前回からのdiffstat．
相変わらず安定しない．．．． :P
[Here's diffstat from previous post.
Hmm, it's kinda unstable code... :P]

 a/vhdl/CCAD.vhd            |  116 -----
 a/vhdl/LOCKD.vhd           |   68 ---
 b/vhdl/DMFx2.vhd           |  112 +++++
 b/vhdl/DMFx8.vhd           |  112 +++++
 b/vhdl/IPFx2.vhd           |  114 +++++
 b/vhdl/IPFx8.vhd           |  114 +++++
 b/vhdl/PLSEXPI.vhd         |  104 ++++
 b/vhdl/QDM_BPF.vhd         |  134 ++++++
 b/vhdl/QM_BPF.vhd          |  143 ++++++
 bench/BENCH_AUGT.vhd       |   56 ++
 bench/BENCH_MODU_DMODU.vhd |   99 ++--
 bench/BENCH_UNPID.vhd      |   60 +-
 bench/DUMB_RF.vhd          |  143 +++++-
 bench/STA.vhd              |   24 -
 bench/STA2STA.vhd          |   12 
 vhdl/AAO_UGT.vhd           |  120 ++---
 vhdl/AGCSTM.vhd            |  441 +++++++++++++------
 vhdl/AGC_CA.vhd            |   71 +--
 vhdl/AGC_FA.vhd            |  119 +++--
 vhdl/AGC_NG.vhd            |  292 ++++++++++---
 vhdl/AUGT.vhd              |   52 +-
 vhdl/DC_BLOCK.vhd          |   51 +-
 vhdl/DMODU.vhd             |  405 ++++--------------
 vhdl/FFT.vhd               |   20 
 vhdl/FPGA1.vhd             |  192 ++++----
 vhdl/FPGA2.vhd             |  999 +++++++++++++++++++++++++++------------------
 vhdl/GPS3_U301.vhd         |   62 ++
 vhdl/GPS3_U801.vhd         |   76 ++-
 vhdl/HARD_MAC.vhd          |    8 
 vhdl/MODU.vhd              |  600 ++++-----------------------
 vhdl/MONSEL1.vhd           |  106 ++--
 vhdl/MONSEL2.vhd           |  496 ++++++++++++----------
 vhdl/NCDLY.vhd             |   36 -
 vhdl/PHY.vhd               |   43 +
 vhdl/PWRC.vhd              |  202 +++++----
 vhdl/ROUND.vhd             |   76 +--
 vhdl/RSSIC.vhd             |   72 ++-
 vhdl/RSSI_AGC.vhd          |  574 ++++++++++++-------------
 vhdl/RX_BBP.vhd            |  405 +++++++++++-------
 vhdl/SYNC_MA.vhd           |   54 +-
 vhdl/TX_BBP.vhd            |  130 ++---
 vhdl/UGT.vhd               |   74 +--
 vhdl/UND_BLOCK.vhd         |   95 ++--
 vhdl/UNI_BLOCK.vhd         |  103 ++--
 vhdl/UNP_BLOCK.vhd         |   28 -
 vhdl/VECTOR.vhd            |   74 ++-
 vhdl/btfly.vhd             |   27 +
 vhdl/outputIF.vhd          |  301 ++++++++-----
 48 files changed, 4517 insertions(+), 3298 deletions(-)

GentooJP.NomiKai++; /* URakuChou */

ナニのついでに有楽町で飲み会．
以下，技術的有用性皆無なメモ．

• 焼き鳥のガツは胃袋．
• パチンコの必勝法は店員と仲良くなる事だが，賭け事はマルチンゲール也．
• "ナガシ"の管理者とかカッコ良さ気．

[NomiKai at URakuChou.
Here is my useless memo.

• T3h "Gatsu" means tripe in YakiTori world.
• A winning strategy Pachinko is to get friendly the stuff, but all gamble is based on martingale.
• Admin of "Nagasi" sounds rock0rz.

]

午前中と飲みが終わってから日付が変わるまで会社にてAGCのパラメータ調整．
-30dBmから-65dBmまで受信したっぽいが，同期検出の相関値に問題有り．
明日，と言うか今日も出社予定也． :P
[This AM and after the Nomikai, I've poke some AGC parameters.
Its reception functionality is now capable of -30dBm to -65dBm as dynamic range.
But yes, it has a PITA WRT sync timing detection's correlation function's value.
SIGNEEDSTOFIX.]